MAX1202 Datasheet, PDF (9/24 Pages) Maxim Integrated Products – 5v, 8-cHANNEL, sERIAL, 12-bIT adcS WITH 3v dIGITAL iNTERFACE

5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
+3.3V
DOUT
3k
DOUT
3k
GND
C_LOAD
C_LOAD
GND
a. High-Z to V_OH and V_OL to V_OH
b. High-Z to V_OL and V_OH to V_OL
Figure 1. Load Circuits for Enable Time
+3.3V
DOUT
3k
DOUT
3k
GND
C_LOAD
C_LOAD
GND
a. V_OH to High-Z
b. V_OL to High-Z
Figure 2. Load Circuits for Disable Time
CS ¹⁸
SCLK ¹⁹
DIN ¹⁷
SHDN ¹⁰
CH0 ¹
CH1 ²
CH2 ³
CH3 ⁴
CH4 ⁵
CH5 ⁶
CH6 ⁷
CH7 ⁸
GND ¹³
REFADJ ¹²
REF ¹¹
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
ANALOG
INPUT
MUX
T/H
MAX1202
MAX1203
CLOCK
IN _12-BIT
SAR
ADC _OUT
REF
+2.44V
REFERENCE
(MAX1202)
A ≈ 1.68
20k
+4.096V
15
DOUT
16 _SSTRB
20 _VDD
14 _VL
9
V_SS
Figure 3. Block Diagram
_______________Detailed Description
The MAX1202/MAX1203 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 12-bit digital output. A flexible ser-
ial interface provides easy interface to 3V microproces-
sors (µPs). Figure 3 is the MAX1202/MAX1203 block
diagram.
Pseudo-Differential Input
Figure 4 shows the ADC’s analog comparator’s sam-
pling architecture. In single-ended mode, IN+ is inter-
nally switched to CH0–CH7 and IN- is switched to
GND. In differential mode, IN+ and IN- are selected
from pairs of CH0/CH1, CH2/CH3, CH4/CH5, and
CH6/CH7. Configure the channels using Tables 3
and 4.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential such that only the signal at IN+ is
sampled. The return side (IN-) must remain stable (typi-
cally within ±0.5LSB, within ±0.1LSB for best results)
with respect to GND during a conversion. To do this,
connect a 0.1µF capacitor from IN- (of the selected
analog input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C_HOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit is entered. The T/H switch opens at the end of
the acquisition interval, retaining charge on C_HOLD as a
sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching C_HOLD from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is sim-
ply GND. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 12-bit resolution.
This action is equivalent to transferring a charge of
16pF x [(V_IN+) - (V_IN-)] from C_HOLD to the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
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