MAX1202 Datasheet, PDF (8/24 Pages) Maxim Integrated Products – 5v, 8-cHANNEL, sERIAL, 12-bIT adcS WITH 3v dIGITAL iNTERFACE

5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
____________________________Typical Operating Characteristics (continued)
(V_DD = 5V ±5%; VL = 2.7V to 3.6V; V_SS = 0V; f_SCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle
(133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, V_REF = 4.096V applied to REF pin; T_A = +25°C;
unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL
1.0
0.8
0.6
0.4
FFT PLOT
20
V_SS = -5V
0
-20
0.2
-40
0
-0.2
-60
-0.4
-80
-0.6
-100
-0.8
-1.0
0
750 1500 2250 3000 3750 4500
DIGITAL CODE
-120
0
33.25
FREQUENCY (kHz)
66.50
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
1–8
CH0–CH7
Sampling Analog Inputs
9
V_SS
Negative Supply Voltage. Tie V_SS to -5V ±5% or to GND.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1202/MAX1203 down to 10µA (max)
10
SHDN
supply current; otherwise, the MAX1202/MAX1203 are fully operational. Pulling SHDN to V_DD puts the
reference-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-
buffer amplifier in external compensation mode.
Reference-Buffer Output/ADC Reference Input. In internal reference mode (MAX1202 only), the refer-
11
REF
ence buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference
mode, disable the internal buffer by pulling REFADJ to V_DD.
12
REFADJ
Input to the Reference-Buffer Amplifier. Tie REFADJ to V_DD to disable the reference-buffer amplifier.
13
GND
Ground; IN- Input for Single-Ended Conversions
14
VL
Supply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of
the Digital Outputs (DOUT, SSTRB). 2.7V ≤ VL ≤ 5.25V.
15
DOUT
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1202/MAX1203 begin
16
SSTRB
the analog-to-digital conversion, and goes high when the conversion is finished. In external clock
mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS
is high (external clock mode).
17
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
18
CS
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
19
SCLK
Serial-Clock Input. SCLK clocks data in and out of the serial interface. In external clock mode, SCLK
also sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
20
V_DD
Positive Supply Voltage, +5V ±5%
8 _______________________________________________________________________________________