MAX1202 Datasheet, PDF (20/24 Pages) Maxim Integrated Products – 5v, 8-cHANNEL, sERIAL, 12-bIT adcS WITH 3v dIGITAL iNTERFACE

5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
FULL POWER-DOWN
1000
2ms FASTPD WAIT
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION
8 CHANNELS
100
10,000
1000
MAX1202/MAX1203
FAST POWER-DOWN
8 CHANNELS
1 CHANNEL
10
1
0
50 100 150 200 250 300 350 400 450 500
CONVERSIONS PER CHANNEL PER SECOND
Figure 14a. MAX1202 Supply Current vs. Sample Rate/Second,
FULLPD, 400kHz Clock
External Reference
With both the MAX1202 and MAX1203, an external refer-
ence can be placed at either the input (REFADJ) or the
output (REF) of the internal reference-buffer amplifier. The
REFADJ input impedance is typically 20kΩ for the
MAX1202, and higher than 100kΩ for the MAX1203,
where the internal reference is omitted. At REF, the DC
input resistance is a minimum of 12kΩ. During conversion,
an external reference at REF must deliver up to 350µA DC
load current and have an output impedance of 10Ω or
less. If the reference has higher output impedance or is
noisy, bypass it close to the REF pin with a 4.7µF capacitor.
Using the buffered REFADJ input makes buffering of the
external reference unnecessary. When connecting an
external reference directly at REF, disable the internal
buffer by tying REFADJ to V_DD. In power-down, the input
bias current to REFADJ can be as much as 25µA with
REFADJ tied to V_DD (MAX1202 only). Pull REFADJ to
GND to minimize the input bias current in power-down.
Transfer Function and Gain Adjust
Figure 15 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 16 shows the bipolar
I/O transfer function. Code transitions occur halfway
between successive-integer LSB values. Output coding
is binary with 1LSB = 1.00mV (4.096V/4096) for unipo-
lar operation, and 1LSB = 1.00mV [(4.096V/2 - -4.096V/
2)/4096] for bipolar operation.
Figure 17 shows how to adjust the ADC gain in applica-
tions that use the internal reference. The circuit provides
±1.5% (±65LSBs) of gain adjustment range.
1 CHANNEL
100
2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50µs WAIT
10
0
2k 4k 6k 8k 10k 12k 14k 16k 18k
CONVERSIONS PER CHANNEL PER SECOND
Figure 14b. MAX1202/MAX1203 Supply Current vs. Sample
Rate/Second, FASTPD, 2MHz Clock
3.0
2.5
2.0
1.5
1.0
0.5
0
0.0001 0.001 0.01 0.1
1
10
TIME IN SHUTDOWN (sec)
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 18 shows the recommended system ground
connections. Establish a single-point analog ground
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