MAX1202 Datasheet, PDF (19/24 Pages) Maxim Integrated Products – 5v, 8-cHANNEL, sERIAL, 12-bIT adcS WITH 3v dIGITAL iNTERFACE

5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
CLOCK
MODE
SETS INTERNAL
CLOCK MODE
INTERNAL CLOCK MODE
SETS FULL
POWER-DOWN
DIN
SXXXXX10
SXXXXX0 0
S
DOUT
DATA VALID
DATA VALID
SSTRB
MODE
CONVERSION
POWERED UP
Figure 12b. Timing Diagram for Power-Down Modes, Internal Clock
CONVERSION
FULL
POWER-DOWN
POWERED
UP
40
35
(V_DD - V_IH) = 2.55V
30
25
20
15
(V_DD - V_IH) = 2.25V
10
(V_DD - V_IH) = 1.95V
5
0
-60 -20 20
60 100 140
TEMPERATURE (°C)
Figure 12c. Additional I_DD Shutdown Supply Current vs. V_IH
for Each Digital Input at a Logic 1
External and Internal References
The MAX1202 can be used with an internal or external
reference, whereas an external reference is required for
the MAX1203. An external reference can be connected
directly at the REF terminal, or at the REFADJ pin.
An internal buffer is designed to provide 4.096V at
REF for both the MAX1202 and the MAX1203. The
MAX1202’s internally trimmed 2.44V reference is
buffered with a gain of 1.68. The MAX1203’s REFADJ
pin is buffered with a gain of 1.64, to scale an external
2.5V reference at REFADJ to 4.096V at REF.
MAX1202 Internal Reference
The MAX1202’s full-scale range using the internal
reference is 4.096V with unipolar inputs and ±2.048V
with bipolar inputs. The internal reference voltage is
adjustable to ±1.5% with the circuit of Figure 17.
COMPLETE CONVERSION SEQUENCE
DIN 1
00
FULLPD
2.5V
REFADJ
0V
4V
REF
0V
(ZEROS)
2ms WAIT
1
01
FASTPD
CH1
1
11
NOPD
τ = RC = 20kΩ x C_REFADJ
t_BUFFEN ≈ 15µs
Figure 13. MAX1202 FULLPD/FASTPD Power-Up Sequence
CH7
1
00
FULLPD
(ZEROS)
1
01
FASTPD
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