MAX1202 Datasheet, PDF (14/24 Pages) Maxim Integrated Products – 5v, 8-cHANNEL, sERIAL, 12-bIT adcS WITH 3v dIGITAL iNTERFACE

5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
CS
SCLK
DIN
DOUT
t_CSS
t_CSH
t_DS
t_DH
t_DV
•••
t_CH
t_CL
•••
•••
•••
Figure 7. Detailed Serial-Interface Timing
t_CSH
t_DO
t_TR
CS
SSTRB
SCLK
•••
t_SDV
•••
•••
t_STR
•••
t_SSTRB
t_SSTRB
•••
•••
PD0 CLOCKED IN
Figure 8. External Clock Mode SSTRB Detailed Timing
The conversion must complete in some minimum time or
droop on the sample-and-hold capacitors might degrade
conversion results. Use internal clock mode if the clock
period exceeds 10µs or if serial-clock interruptions could
cause the conversion interval to exceed 120µs.
Internal Clock
In internal clock mode, the MAX1202/MAX1203 generate
their own conversion clock. This frees the µP from run-
ning the SAR conversion clock, and allows the con-
version results to be read back at the processor’s
convenience, at any clock rate from zero to 2MHz.
SSTRB goes low at the start of the conversion, then goes
high when the conversion is complete. SSTRB is low for
a maximum of 10µs, during which time SCLK should
remain low for best noise performance. An internal regis-
ter stores data while the conversion is in progress. SCLK
clocks the data out at this register at any time after the
conversion is complete. After SSTRB goes high, the next
falling clock edge produces the MSB of the conversion
at DOUT, followed by the remaining bits in MSB-first for-
mat (Figure 9). CS does not need to be held low once a
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