MAX101A Datasheet, PDF (9/16 Pages) Maxim Integrated Products – 500Msps, 8-Bit ADC with Track/Hold

500Msps, 8-Bit ADC with Track/Hold
CLK
N–1
N
N+1 N+2
DCLK
0
1
+14 +15 +16 +17
7
8
ADATA
N-1
N+1
N+3
BDATA
tPD2
t_PD2
N-2
N
N+2
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE INPUT CLOCK PHASING SECTION.
Figure 2. Output Timing, Clock to Data, Normal Mode (DIV10 = OPEN)
N
N+1 N+2 N+3
CLK
DCLK
+15 +16 +17
ADATA
BDATA
N
N+5
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE INPUT CLOCK PHASING SECTION.
Figure 3. Output Timing, Test Mode (DIV10 = GND)
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