MAX101A Datasheet, PDF (8/16 Pages) Maxim Integrated Products – 500Msps, 8-Bit ADC with Track/Hold

500Msps, 8-Bit ADC with Track/Hold
_________________________________________________Pin Description (continued)
PIN
50
51
52
53
54
55
65
66
72, 73
75, 76
83
NAME
VART
VARTS
TP1
TP2
VARBS
VARB
TP5
TP6
AIN+
AIN-
PHADJ
FUNCTION
“A” side positive reference voltage input (Note 9)
“A” side positive reference voltage sense (Note 9)
Internal connection, leave pin open.
Internal connection, leave pin open.
“A” side negative reference voltage sense (Note 9)
“A” side negative reference voltage input (Note 9)
Internal connection, leave pin open.
Internal connection, leave pin open.
Analog Inputs, internally terminated with 50Ω to ground. Full-scale linear input range is approximately
±250mV. Drive AIN+ and AIN- differentially for best high-frequency performance.
Phase adjustment for T/H. Normally connected to ground. A phase adjustment of approximately ±18ps
can be made by varying this pin’s bias point to optimize interleaving between sides A and B (Note 10).
Note 9: VART, VARB, VBRT, and VBRB should be adjusted separately from a well bypassed reference circuit to ensure proper
amplitude and offset matching. The sense connections to each of these terminals allows precision setting of the reference
voltage. The reference ladder is similar for both converter halves (check electrical section for values). Any noise on these
terminals will severely reduce overall performance.
Note 10: Good results are obtained by connecting the PHADJ input to ground. Improve performance by applying a voltage between
±1.25V to this input. The time that the “A” T/H bridge samples relative to the time that the “B” T/H bridge samples can be
varied through a ±18ps range.
CLK
CLK
DCLK
DCLK
ADATA
tPWH
tPD1
tPWL
BDATA
tPD2
tPD2
Figure 1. Output Timing, Normal Mode (DIV10 = OPEN)
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