MAX101A Datasheet, PDF (4/16 Pages) Maxim Integrated Products – 500Msps, 8-Bit ADC with Track/Hold

500Msps, 8-Bit ADC with Track/Hold
TIMING CHARACTERISTICS
(VEE = -5.2V, VCC = +5V, RL = 100Ω to -2V, VART, VBRT = 0.95V, VARB, VBRB = -0.95V, TA = +25°C, unless otherwise noted.)
PARAMETER
Clock Pulse Width Low
Clock Pulse Width High
CLK to DCLK
Propagation Delay
SYMBOL
tPWL
tPWH
CLK, CLK
CLK, CLK
CONDITIONS
tPD1 DIV10 = 0, Figures 1 and 2
MIN TYP MAX UNITS
0.9
2.5
ns
0.9
2.5
ns
1.2
2.3
3.4
ns
DCLK to A/BData
Propagation Delay
Rise Time
Fall Time
Pipeline Delay (Latency)
tPD2
tR
tF
tNPD
DIV10 = 0, Figures 1 and 2
20% to 80%
DCLK
DATA
20% to 80%
DCLK
DATA
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0.7
1.3
1.8
ns
300
ps
500
300
ps
800
15
15
Clock
Cycles
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
All devices are 100% production tested at +25°C and are guaranteed by design for TA = TMIN to TMAX as specified.
Deviation from best-fit straight line. See Integral Nonlinearity section.
See the Signal-to-Noise Ratio and Effective Bits section in the Detailed Description of Specifications.
SNR calculated from effective bits performance using the following equation: SNR(dB) = 1.76 + 6.02 x effective bits.
Clock pulse width minimum requirements tPWL and tPWH must be observed to achieve stated performance.
Outputs terminated through 100Ω to -2.0V.
__________________________________________Typical Operating Characteristics
(VEE = -5.2V, VCC = +5V, RL = 100Ω to -2V, VART, VBRT = 0.95V, VARB, VBRB = -0.95V, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.75
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.75
0.50
0.50
0.25
0.25
0
-0.25
0
-0.25
-0.50
-0.75
0
64
128
192
256
OUTPUT CODE
-0.50
-0.75
0
64
128
192
256
OUTPUT CODE
4 _______________________________________________________________________________________