MAX101A Datasheet, PDF (12/16 Pages) Maxim Integrated Products – 500Msps, 8-Bit ADC with Track/Hold

500Msps, 8-Bit ADC with Track/Hold
Table 2. Input Voltage Range
INPUT
Differential
Single
Ended
AIN+
(mV)
+125
0
-125
+250
0
-250
AIN-
(mV)
-125
0
+125
0
0
0
OUTPUT
CODE
MSB to
LSB
1 1 1 1 1 1 1 1 full scale
1 0 0 0 0 0 0 0 mid scale
0 0 0 0 0 0 0 0 zero scale
1 1 1 1 1 1 1 1 full scale
1 0 0 0 0 0 0 0 mid scale
0 0 0 0 0 0 0 0 zero scale
* An offset VIO, as specified in the DC electrical parameters, will
be present at the input. Compensate for this offset by adjusting
the reference voltage. Offsets may be different between side A
and side B.
For single-ended operation:
1) Apply a DC offset to one of the analog inputs, or
leave one input open. (Both AIN+ and AIN- are ter-
minated internally with 50Ω to analog ground.)
2) Drive the other input with a ±250mV + offset to
obtain either full- or zero-scale digital output. If a DC
common-mode offset is used, the total voltage swing
allowed is ±500mV (analog signal plus offset with
respect to ground).
Reference
The ADC’s reference resistor is a Kelvin-sensed, resis-
tor string that sets the ADC’s LSB size and dynamic
operating range. Normally, the top and bottom of this
string are driven with an external buffer amplifier. It will
need to supply approximately 19mA due to the 100Ω
minimum resistor string impedance. A ±0.95V refer-
ence voltage is normally applied to inputs VART, VBRT,
VARB, and VBRB. The reference inputs VARTS, VARBS,
VBRTS, and VBRBS allow Kelvin sensing of the applied
voltages to increase precision.
An RC network at the ADC’s reference terminals is
needed for best performance. This network consists of
a 33Ω resistor connected in series with the buffer out-
put that drives the reference. A 0.47µF capacitor must
be connected near the resistor at the buffer’s output
(see Typical Operating Circuit). This resistor and
capacitor combination should be located within 0.5
inches of the MAX101A package. Any noise on these
pins will directly affect the code uncertainty and
degrade the ADC’s effective-bits performance.
POSITIVE
REFERENCE
VART
VARTS
PARASITIC
RESISTANCE
R
TO
COMPARATORS
R
R
R
VARBS
VARB
NEGATIVE
REFERENCE
R
PARASITIC
RESISTANCE
Figure 5. Reference Ladder
12 ______________________________________________________________________________________