MAX101A Datasheet, PDF (7/16 Pages) Maxim Integrated Products – 500Msps, 8-Bit ADC with Track/Hold

500Msps, 8-Bit ADC with Track/Hold
______________________________________________________________Pin Description
PIN
1
2, 62
3, 61
4, 7, 15, 18,
24, 27, 30,
34, 37, 40,
46, 49, 57,
60, 64, 67,
68, 70, 71,
74, 77, 78,
79, 82, 84
5, 59
6, 58
8, 21, 43,
56, 81
9
10
11
12
13
14
16, 48, 63
29
31
33
32, 69, 80
35
36, 38, 39,
41, 42, 44,
45, 47
28, 26, 25,
23, 22, 20,
19, 17
NAME
PAD
CLK
CLK
GND
TRK1
TRK1
VCC
VBRB
VBRBS
TP4
TP3
VBRTS
VBRT
N.C.
SUB
DCLK
DCLK
VEE
DIV10
A7–A0
B7–B0
Internal connection, leave open.
FUNCTION
Complementary Differential Clock Inputs. Can be driven from standard 10KH ECL with the following
considerations: Internally, pins 2, 62 and 3, 61 are the ends of a 50Ω transmission line. Either end
can be driven with the other end terminated with 50Ω to -2V. See Typical Operating Circuit.
Power-Supply Ground
Phasing inputs (normally left open). See Applications Information section.
Positive Power Supply, +5V ±5% nominal
“B” side negative reference voltage input (Note 9)
“B” side negative reference voltage sense (Note 9)
Internal connection, leave pin open.
Internal connection, leave pin open.
“B” side positive reference voltage sense (Note 9)
“B” side positive reference voltage input (Note 9)
No Connect—no internal connection to these pins.
Circuit Substrate contact. This pin must be connected to VEE.
Complementary Differential Clock Outputs. Used to synchronize following circuitry: Outputs A0–A7
are valid after DCLK’s rising edge. B0–B7 output data are valid after DCLK’s falling edge (see Figure 1
for output timing information).
Negative Power Supply, -5.2V ±5% nominal
Divide by 10 mode. Leave open for normal operation. Selects test mode when grounded.
AData and BData Outputs. A0 and B0 are the LSBs, and A7 and B7 are the MSBs. AData and BData
outputs conform to ECL logic swings and drive 100Ω transmission lines. Terminate with 100Ω to -2V
(120Ω for Tj > +100°C). See Figures 1–3.
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