DS80C400_09 Datasheet, PDF (82/97 Pages) Maxim Integrated Products – Network Microcontroller

DS80C400 Network Microcontroller
Table 21. Arbitration/Masking Feature Summary
TEST NAME
ARBITRATION
REGISTERS
MASK REGISTERS
Standard 11-bit
Arbitration
(CAN 2.0A)
Message Center
Arbitration Registers 0–1
(Located in each message
center, MOVX memory)
Standard Global Mask
Registers 0–1 (Located in
CAN control/status/mask
register bank, MOVX
memory)
Extended 29-bit
Arbitration
(CAN 2.0B)
Message Center
Arbitration Registers 0–3
(Located in each message
center, MOVX memory)
Extended Global Mask
Registers 0–3 (Located in
CAN control/status/mask
register bank, MOVX
memory)
Media Byte
Arbitration
Media Arbitration Registers
0–3 (Located in CAN
control/status/mask
register bank, MOVX
memory)
Media ID Mask Registers
0–1 (Located in CAN
control/status/mask
register bank, MOVX
memory)
Message Center
15, Standard 11-
bit Arbitration
(CAN 2.0A)
Message Center 15
Arbitration Registers 0–1
(Located in message
center 15, MOVX memory)
Message Center 15 Mask
Registers 0–1 (Located in
CAN control/status/mask
register bank, MOVX
memory)
Message Center
15, Extended
29-bit Arbitration
(CAN 2.0B)
Message Center 15
Arbitration Registers 0–3
(Located in message
center 15, MOVX memory)
Message Center 15 Mask
Registers 0–3 (Located in
CAN control/status/mask
register bank, MOVX
memory)
CONTROL BITS
AND CONDITIONS
EX/ST = 0
MEME = 0: Mask register ignored. ID and
arbitration register must match exactly.
MEME = 1: Only bits corresponding to 1 in
mask register are compared in ID and
arbitration registers.
EX/ST = 1
MEME = 0: Mask register ignored. ID and
arbitration register must match exactly.
MEME = 1: Only bits corresponding to 1 in
mask register are compared in ID and
arbitration registers.
MDME = 0: Media byte arbitration disabled.
MDME = 1: Only bits corresponding to 1 in
Media ID mask register are compared
between data bytes 1 and 2 and Media
arbitration registers.
EX/ST = 0
MEME = 0: Mask register ignored. ID and
arbitration register must match exactly.
MEME = 1: Message center 15 mask
registers are ANDed with Global Mask
register. Only bits corresponding to 1 in
resulting value are compared in ID and
arbitration registers.
EX/ST = 1
MEME = 0: Mask register ignored. ID and
arbitration register must match exactly.
MEME = 1: Message center 15 mask
registers are ANDed with Global Mask
register. Only bits corresponding to 1 in
resulting value are compared in ID and
arbitration registers.
Message Buffering/Overwrite
If a message center is configured for reception (T/R = 0) and the previous message has not been read (DTUP = 1),
then the disposition of an incoming message to that message center is controlled by the WTOE bit (located in CAN
arbitration register 3 of each message center). When WTOE = 0, the incoming message is discarded and the
current message untouched.
If the WTOE bit is set, the incoming message is received and written over the existing data bytes in that message
center. The receiver overwrite bit (ROW) also is set in the corresponding message center control register, located
in SFR memory.
Message center 15 is unique in that it incorporates a buffer that can receive up to two messages without loss. If a
message is received by message center 15 while it contains an unread message, the new incoming message is
held in an internal buffer. When the CAN controller reads the message center 15 memory location and then clears
DTUP = INTRQ = EXTRQ = 0, the contents of the internal buffer are automatically loaded into the message center
15 MOVX memory location.
The message center 15 WTOE bit controls what happens if a third message is received when both the message
center 15 MOVX memory location and the buffer contain unread messages. If WTOE = 0, the new message is
discarded, leaving the message center 15 MOVX memory location and the buffer untouched. If WTOE = 1, then
the third message writes over the buffered message but leaves the message center 15 MOVX memory location
untouched.
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