DS80C400_09 Datasheet, PDF (60/97 Pages) Maxim Integrated Products – Network Microcontroller

DS80C400 Network Microcontroller
Media Independent Interface (MII)
The DS80C400 contains an IEEE 802.3 MII-compliant PHY interface. This interface contains two basic blocks. The
MII I/O block provides independent transmit and receive data-path I/O and PHY network-status signal inputs. The
MII management block implements a 2-wire serial communication bus to facilitate PHY register access. The block
diagram in Figure 4 shows the signals associated with the DS80C400 MII.
Figure 4. MII Block Diagram
EXTERNAL
PHY
DEVICE
TXCLK
TX_EN
TXD[3:0]
RXCLK
RX_DV
RX_ER
RXD[3:0]
CRS
COL
MDC
MDIO
MII I/O BLOCK
(TRANSMIT,
RECEIVE, AND FLOW
CONTROL)
MII
MANAGEMENT
BLOCK
(SERIAL INTERFACE
BUS TO PHY)
DS80C400
NOTE: WHEN CONNECTING THE DS80C400 TO AN EXTERNAL PHY, DO NOT CONNECT THE RSTOL TO THE RESET OF THE PHY. DOING SO
MAY DISABLE THE ETHERNET TRANSMIT.
MII Management Block
The MII management block allows the host to write control data to and read status from any of 32 registers in any
of 32 PHY controllers. The MII management block communicates with external PHY(s) over a 2-wire serial
interface composed of the MDC serial-clock output pin and the MDIO pin that serves as the I/O line for all address
and data transactions. Data (MDIO) is valid on the rising edge of clock (MDC). The MII address (14h) and MII data
(18h) CSR registers, outlined previously in the CSR Register section, are used by the CPU to monitor and control
the 2-wire MII serial bus. A write to the CSR register MII address triggers the read or write operation. Figure 5
shows the MII management frame format.
Figure 5. MII Management Frame Format
READ
WRITE
PREAMBLE
(32 bits)
111…111
111…111
START
(2 bits)
01
01
OP CODE PHY ADDRESS
(2 bits)
(5 bits)
10
PHYA [4:0]
01
PHYA [4:0]
PHY
REGISTER
(5 bits)
PHYR[4:0]
PHYR[4:0]
TURN
AROUND
(2 bits)
ZZ^*
10
DATA
(16 bits)
ZZ….ZZ^*
PHYD[15:0]
IDLE
(1 bit)
Z
Z
*During a read operation, the external PHY drives the MDIO line low for the second bit of the turnaround field to indicate proper synchronization,
and then drives the 16-bits of read data requested.
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