DS80C400_09 Datasheet, PDF (51/97 Pages) Maxim Integrated Products – Network Microcontroller

DS80C400 Network Microcontroller
aborted. The BCU incorporates a 31 x 8 first-in-first-out receive packet register (receive FIFO) so that the CPU can
access information for the next receive packet in queue. Upon reception of each valid packet into receive buffer
memory, the BCU writes a receive status word into the first word of the receive packet starting page, updates the
receive FIFO, and notifies the CPU by setting an interrupt flag. The CPU can access the receive FIFO by reading
the BCUD SFR. Bits 4–0 of the data read from BCUD contain the starting page address and bits 7, 6, 5 reflect the
number of pages occupied by the packet.
For a transmit operation, the tasks performed by the BCU are similar. The CPU first provides size/location
information of the transmit packet to the BCU. This is accomplished by three consecutive writes to the BCUD SFR.
The first write specifies the MSB of the 11-bit byte count for the transmit packet, the second gives the LSB of the
11-bit byte count, and the third provides the starting page address for the packet. Note that at page 31 of the
transmit buffer, the next consecutive page is page (n). The CPU issues a transmit request to the BCU, which then
communicates this request to the MAC. Once started, the BCU reads data from transmit buffer memory and feeds
the data to the MAC for presentation on the MII. This process continues until the transaction is complete or the
transmission is aborted. The BCU then writes a transmit status word back to transmit buffer memory and notifies
the CPU by setting the interrupt flag. Transmit buffer management should be handled by the application code.
Command/Status (CSR) Registers
The CSR registers are essential in defining the operational characteristics of the Ethernet controller. The CSR
registers contain the following key items:
 MAC physical address
 Transmit, receive, and flow control settings for the MAC
 Multicast hash table used by the address check block
 Filter mode and good/bad frame controls for the address check block
 VLAN tag identifiers
 Wake-up frame filter
 Register interface for serial MII PHY management bus
Each CSR register is 32-bits wide and is accessible using the BCUC, CSRA, CSRD SFR interface described in the
Buffer Control Unit section. To program a CSR register, the application code must provide data (CSRD) and
address (CSRA) for the target register before issuing the ‘Write CSR Register’ command to the BCU. When
performing a CSR register read, the application code provides the address (CSRA), issues the ‘Read CSR
Register’ command to the BCU, and then may unload the data (CSRD). The sequences below illustrate the correct
procedures for writing and reading the CSR registers.
CSR Register Write
Load CSRD with MSB of 32-bit word to be written.
Load CSRD with LSB + 2 of the 32-bit word to be written.
Load CSRD with LSB + 1 of the 32-bit word to be written.
Load CSRD with LSB of the 32-bit word to be written.
Load CSRA with address of the CSR register to be written.
Issue the ‘Write CSR Register’ command to the BCU by writing BCUC.3–BCUC.0 = 1000b.
CSR Register Read
Load CSRA with address of the CSR register to be read.
Issue the ‘Read CSR Register’ command to the BCU by writing BCUC.3–BCUC.0 = 1001b.
Wait until the BCU busy bit (BCUC.7) = 0.
Unload CSRD for the MSB of the 32-bit word.
Unload CSRD for the LSB + 2 of the 32-bit word.
Unload CSRD for the LSB + 1 of the 32-bit word.
Unload CSRD for the LSB of the 32-bit word.
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