DS80C400_09 Datasheet, PDF (64/97 Pages) Maxim Integrated Products – Network Microcontroller

DS80C400 Network Microcontroller
Transmit/Receive Packet Buffer Memory (8kB)
The DS80C400 Ethernet controller uses 8kB of internal SRAM as transmit/receive packet buffer memory. This
SRAM is read/write accessible as data memory by the CPU using the MOVX instruction. The BCU also has access
to this SRAM, and automatically writes/reads packet buffer memory whenever it needs to store or retrieve Ethernet
packet information. The logical MOVX address range of the 8kB SRAM is determined by the IDM1:0 bits of the
MCON (C6h) SFR. Table 16 shows the available address range settings.
When used for Ethernet packet buffer memory, the 8kB SRAM is logically configured into (32) pages of 64 words
each, where a word consists of 4 Bytes. These 32 pages can be dynamically allocated between Ethernet transmit
and receive buffer memory. The five least significant bits of the Ethernet buffer size (EBS; E5h) SFR specify how
many pages are allocated for receive buffer memory. The remaining pages of the 32 are used as transmit buffer
memory. Note that transmit and receive data packets can span multiple pages. The reset default state of the
Ethernet buffer size select bits (EBS.4–EBS.0) is 00000b, which configures all 32 pages as transmit buffer
memory. As an example, setting EBS.4–EBS.0 = 10000b would result in pages 0–15 (16 pages) being configured
as receive buffer memory and pages 16–31 (16 pages) being configured as transmit buffer memory. A setting of
11111b leaves a single page (page 31) for transmit buffer memory and configures pages 0–30 (31 pages) as
receive buffer memory. Changing the transmit/receive buffer-size settings flush the contents of the receive buffer
and the receive FIFO. Figure 10 is an illustration of the 8kB buffer memory map and addressing scheme.
Table 16. Packet Buffer Memory Location
IDM1:0
(MCON.7, MCON.6)
00
01
10
11
INTERNAL 8kB SRAM LOCATION
(ETHERNET PACKET BUFFER MEMORY)
00E000h–00FFFFh
000000h–001FFFh
FFE000h–FFFFFFh
Reserved
Figure 10. Transmit/Receive Data Buffer Memory
RECEIVE
BUFFER
(n PAGES)
8kB INTERNAL SRAM
PAGE 0
PAGE 1
.
.
.
.
.
.
BUFFER SIZE
SETTING
(EBS.4–EBS.0)
TRANSMIT
BUFFER
(32 - n PAGES)
PAGE (n - 2)
PAGE (n - 1)
PAGE n
.
.
.
PAGE 31
PAGE 1
STATUS WORD (WORD 0)
WORD 1
WORD 2
.
.
.
.
WORD 63
BUFFER MEMORY ADDRESS (24-Bit)
(Per IDM1:0)
PAGE WORD BYTE
EXAMPLE: PAGE 1, WORD 2, BYTE 3
xxxxxxxx xxx
00001 000010 11
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