DS80C400_09 Datasheet, PDF (31/97 Pages) Maxim Integrated Products – Network Microcontroller

DS80C400 Network Microcontroller
PIN
NAME
FUNCTION
51
P6.5
P6.1
P6.2
CE5 Program Memory Chip Enable 5
CE6 Program Memory Chip Enable 6
50
P6.6
P6.3
P6.4
CE7 Program Memory Chip Enable 7
A20 Program/Data Memory Address 20
P6.5 A21 Program/Data Memory Address 21
49
P6.7
P6.6 RXD2 Serial Port 2 Receive
P6.7 TXD2 Serial Port 2 Transmit
78
A0
Port 7, I/O. Port 7 can function as either an 8-bit, bidirectional I/O port or the nonmultiplexed A0–A7 signals
(when the MUX pin = 1). The reset condition of Port 7 is all bits at logic 1 through a weak pullup. The logic 1
77
A1
state also serves as an input mode, since external circuits writing to the port can override the weak pullup.
When software clears any port pin to 0, a strong pulldown is activated that remains on until either a 1 is written
to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition driver,
76
A2
followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again
becomes the output (and input) high state.
75
A3
Port
Alternate Function
74
A4
P7.0 A0 Program/Data Memory Address 0
P7.1 A1 Program/Data Memory Address 1
73
A5
P7.2 A2 Program/Data Memory Address 2
P7.3 A3 Program/Data Memory Address 3
72
A6
P7.4
P7.5
A4 Program/Data Memory Address 4
A5 Program/Data Memory Address 5
71
A7
P7.6
P7.7
A6 Program/Data Memory Address 6
A7 Program/Data Memory Address 7
Transmit Clock, Input. The transmit clock is a continuous clock sourced from the Ethernet PHY controller. It is
used to provide timing reference for transferring of TX_EN and TXD[3:0] signals from the MAC to the external
8
TXClk
Ethernet PHY controller. The input clock frequency of TXClk should be 25MHz for 100Mbps operation and
2.5MHz for 10Mbps operation. For ENDEC operation, TXClk serves the same function, but the input clock
frequency should be 10MHz.
Transmit Enable, Output. The transmit enable is an active-high output and is synchronous with respect to the
TXClk signal. TX_EN is used to indicate valid nibbles of data for transmission on the MII pins TXD.3–TXD.0.
7
TX_EN TX_EN is asserted with the first nibble of the preamble and remains asserted while all nibbles to be transmitted
are presented on the TXD.3–TXD.0 pins. TX_EN negates prior to the first TXClk following the final nibble of the
frame. TX_EN serves the same function for ENDEC operation.
3
TXD.3
Transmit Data, Output. The transmit data outputs provide 4-bit nibbles of data for transmission over the MII.
4
5
TXD.2
TXD.1
The transmit data is synchronous with respect to the TXClk signal. For each TXClk period when TX_EN is
asserted, TXD.3–TXD.0 provides the data for transmission to the Ethernet PHY controller. When TX_EN is
deasserted, the TXD data should be ignored. For ENDEC operation, only TXD.0 is used for transmission of
6
TXD.0
frames.
Receive Clock, Input. The receive clock is a continuous clock sourced from the Ethernet PHY controller. It is
used to provide timing reference for transferring of RX_DV, RX_ER, and RXD[3:0] signals from the external
10
RXClk
Ethernet PHY controller to the MAC. The input clock frequency of RXClk should be 25MHz for 100Mbps
operation and 2.5MHz for 10Mbps operation. For ENDEC operation, RXClk serves the same function, but the
input clock frequency should be 10MHz.
Receive Data Valid, Input. The receive data valid is an active-high input from the external Ethernet PHY
controller and is synchronous with respect to the RXClk signal. RX_DV is used to indicate valid nibbles of data
11
RX_DV for reception on the MII pins RXD.3–RXD.0. RX_DV is asserted continuously from the first nibble of the frame
through the final nibble. RX_DV negates prior to the first RXClk following the final nibble. RX_DV serves the
same function for ENDEC operation.
Receive Error, Input. The receive error is an active-high input from the external Ethernet PHY controller and is
synchronous with respect to the RXClk signal. RX_ER is used to indicate to the MAC that an error (e.g., a
9
RX_ER coding error, or any error detectable by the PHY) was detected somewhere in the frame presently being
transmitted by the PHY. RX_ER has no effect on the MAC while RX_DV is deasserted. RX_ER should be low
for ENDEC operation.
17
RXD.3
Receive Data, Input. The receive data inputs provide 4-bit nibbles of data for reception over the MII. The
16
RXD.2
receive data is synchronous with respect to the RXClk signal. For each RXClk period when RX_DV is asserted,
15
RXD.1
RXD.3–RXD.0 have the data to be received by the MAC. When RX_DV is deasserted, the RXD data should be
14
RXD.0
ignored. For ENDEC operation, only RXD.0 is used for reception of frames.
Carrier Sense, Input. The carrier sense signal is an active-high input and should be asserted by the external
Ethernet PHY controller when either the transmit or receive medium is not idle. CRS should be deasserted by
1
CRS
the PHY when the transmit and receive mediums are idle. The PHY should ensure that the CRS signal remains
asserted throughout the duration of a collision condition. The transitions on the CRS signal need not be
synchronous to TXClk or RXClk. CRS serves the same function for ENDEC operation.
Collision Detect, Input. The collision detect signal is an active-high input and should be asserted by the
external Ethernet PHY controller upon detection of a collision on the medium. The PHY should ensure that COL
2
COL
remains asserted while the collision condition persists. The transitions on the COL signal need not be
synchronous to TXClk or RXClk. The COL signal is ignored by the MAC when operating in full-duplex mode.
COL serves the same function for ENDEC operation.
18
MDC
MII Management Clock, Output. The MII management clock is generated by the MAC for use by the external
Ethernet PHY controller as a timing referenced for transferring information on the MDIO pin. MDC is a periodic
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