DSSHA1 Datasheet, PDF (8/9 Pages) Maxim Integrated Products – Memory-Mapped SHA-1 Coprocessor Five 32-Bit Registers to Read MAC Result

Memory-Mapped SHA-1 Coprocessor
Physical Estimates
• Gate count 6,423 (NAND 2x1 used for calculation).
• Area is 85,470µm² without routing.
• Area is 102,256µm² with routing estimate.
Library used for estimate:
ARM TSMC CL018G (0.18um generic process) 1.8V
SAGE-X standard cells library, version 2004q3v1. The
ARM part number is A0082. This is a free, foundry-
sponsored library that can be obtained at:
www.arm.com/products/physicalip/productsservices.html.
Verification
The industry typically denotes the level of verification of
an IP block with the following conventions:
• Gold IP has been to target silicon.
• Silver IP has been to target silicon in FPGA.
• Bronze IP has been verified in silicon models with
logical timing closure.
• In-development IP has not yet been verified.
Note: The DSSHA1 has achieved silver status.
Deliverables
The DSSHA1 package comes complete with:
• Verilog HDL
• Verilog Test Bench
• Readme Information on Setup and Scripts
The free DSSHA1 IP is available by request at
https://support.maxim-ic.com/1-Wire.
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