DSSHA1 Datasheet, PDF (2/9 Pages) Maxim Integrated Products – Memory-Mapped SHA-1 Coprocessor Five 32-Bit Registers to Read MAC Result

Memory-Mapped SHA-1 Coprocessor
Description
The DSSHA1 is a synthesizable, memory-mapped
SHA-1 coprocessor that includes a 64-byte general-
purpose RAM that stores the 64-byte message. The
input message is used to compute the SHA-1 MAC.
The DSSHA1 input and output port signals are
designed to internally connect to a 32-bit bus.
Implementation in an ASIC or FPGA provides a SHA-1
hash only to be compared to the SHA-1 hash of Maxim
devices. By a positive comparison result, authentication
security is achieved between a host system and slave
accessories. Maxim has numerous SHA-1 slave
devices such as the DS28E01-100 and DS28E10
1-Wire^® devices, the DS1961S and DS1963S iButton^®
devices, and the DS28CN01 I²C device.
Figure 1 shows how the 64-byte SHA-1 message is
inserted into the RAM. Triggering the input signal
RUN_SHA to logic-high starts the SHA-1 computation.
The output BUSY signal indicates an occurring com-
putation. Upon completion of the BUSY signal, the
result registers contain the 20-byte message digest
for reading.
RSTZ
RST
RAM_DATAO
SHA-1
INITIAL
CLK
WRZ
CSZ
DATAI[31:0]
ADDR[4:0]
RUN_SHA
SHA-1 RAM
64 BYTES
SHA-1 RESULT
20-BYTE MAC
RESULT_DATAO
A, B, C,
D, E
RAM_ADDR[4]
GLUE LOGIC
RAM_ADDR
RAM_DATAI
SHA-1
ENGINE
DSSHA1
DATAO[31:0]
BUSY
Figure 1. Block Diagram
1-Wire and iButton are registered trademarks of Maxim Integrated Products, Inc.
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