DSSHA1 Datasheet, PDF (3/9 Pages) Maxim Integrated Products – Memory-Mapped SHA-1 Coprocessor Five 32-Bit Registers to Read MAC Result

Memory-Mapped SHA-1 Coprocessor
Signal Description
NAME
TYPE*
FUNCTION
CLK
I Clock. On the positive edge, data on signals DATAI[31:0] and DATAO[31:0] are clocked in and out.
RSTZ
I
Active-Low Reset. The RSTZ signal is evaluated at each interval of the positive edge of the CLK
signal. It is necessary to do a reset before every load of a 512-bit message and MAC computation.
CSZ
I Active-Low Chip Select. This signal must be low for all accesses to registers and memory.
WRZ
ADDR[4:0]
I Active-Low Write Enable. This signal must be low during all write operations.
I Address[4:0]. These five signals are the address signals.
DATAI[31:0]
I Data Bus Input. These 32 signals are the input data bus.
DATAO[31:0]
O Data Bus Output. These 32 signals are the output data bus.
BUSY
O
Busy. When high, this signal indicates that the SHA-1 coprocessor is busy performing a computation.
There should be no data accesses while this signal is high.
RUN_SHA
I
Run SHA-1. This signal must only be one clock period wide and initiates a SHA-1 computation upon
the positive edge of the CLK signal.
*I = Input, O = Output.
Memory Map
ADDRESS (HEX)
0x00 to 0x0F
0x10 to 0x14
TYPE
RAM
Registers
ACCESS
FUNCTION
64-Byte Buffer Input. This is the 512-bit input block that usually includes the
Read/Write 64-bit slave device secret and a 448-bit input message consisting of a random
challenge and various data.
Read
20-Byte Result. This is the MAC for comparison to the received MAC of the
SHA-1 slave device.
Detailed Register Description
Input Buffer (00h to 0Fh)
The SHA-1 engine receives the data to be processed
through the 64-byte input buffer. This buffer holds the
512-bit message that the SHA-1 engine processes to
generate a MAC. Secret and other message data are
contained in the input buffer. Security of the secret is a
task left for the designer. The format of the data is
defined by each Maxim SHA-1 slave device.
MAC Result (10h to 14h)
A 20-byte MAC of a SHA-1 computation resides in the
MAC result address space.
Device Operation
The typical use of the DSSHA1 in an application
involves writing, reading, and running the SHA-1
engine, and using the MAC result to externally compare
this block to the MAC of a 1-Wire SHA-1 device. All
these activities are controlled through the 32-bit inter-
face with separate data input and output lines to easily
connect to the internal bus inside an ASIC or FPGA.
The SHA-1 Engine Control section explains the data
input and output format and how to instruct the SHA-1
engine to perform a MAC computation.
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