DSSHA1 Datasheet, PDF (5/9 Pages) Maxim Integrated Products – Memory-Mapped SHA-1 Coprocessor Five 32-Bit Registers to Read MAC Result

Memory-Mapped SHA-1 Coprocessor
Table 2 shows how the five 32-bit variables A to E that
hold the MAC are mapped to the respective locations.
Table 2. Output Message Format
ADDRESS (HEX) MAC RESULT REGISTERS (MRR)
10
MRR[31:0] = A[31:0]
11
MRR[31:0] = B[31:0]
12
MRR[31:0] = C[31:0]
13
MRR[31:0] = D[31:0]
14
MRR[31:0] = E[31:0]
MAC Comparison
The master has the requirement to test the slave MAC
against the DSSHA1 MAC. Authenticity is verified if the
slave MAC and the DSSHA1 MAC are equal in value. A
fraud is verified if the slave MAC and the DSSHA1 MAC
are different.
Functional Verification
To test the DSSHA1, the test message “abc” can verify
functionality. This test message with proper padding
can be translated into an input block of:
W[0] = 61626380
W[8] = 00000000
W[1] = 00000000
W[9] = 00000000
W[2] = 00000000
W[10] = 00000000
W[3] = 00000000
W[11] = 00000000
W[4] = 00000000
W[12] = 00000000
W[5] = 00000000
W[13] = 00000000
W[6] = 00000000
W[14] = 00000000
W[7] = 00000000
W[15] = 00000018
Using the table format from Table 1, the input block of
this test message will be the values in Table 3.
The output of the computation of this block is:
Output[0] = 42541B35
Output[1] = 5738D5E1
Output[2] = 21834873
Output[3] = 681E6DF6
Output[4] = D8FDF6AD
The Maxim devices take these words as most signifi-
cant word first and the individual bytes as least signifi-
cant byte (LSB) first. So the device ordering of the
output would be:
AD F6 FD D8 F6 6D 1E 68 73 48 83 21 E1 D5 38 57 35 1B 54 42
Table 3. SHA-1 Input for “abc” Test Packet
M0[31:24] = 61h
M0[23:16] = 62h
M0[15:8] = 63h
M0[7:0] = 80h
M1[31:24] = 00h
M1[23:16] = 00h
M1[15:8] = 00h
M1[7:0] = 00h
M2[31:24] = 00h
M2[23:16] = 00h
M2[15:8] = 00h
M2[7:0] = 00h
M3[31:24] = 00h
M3[23:16] = 00h
M3[15:8] = 00h
M3[7:0] = 00h
M4[31:24] = 00h
M4[23:16] = 00h
M4[15:8] = 00h
M4[7:0] = 00h
M5[31:24] = 00h
M5[23:16] = 00h
M5[15:8] = 00h
M5[7:0] = 00h
M6[31:24] = 00h
M6[23:16] = 00h
M6[15:8] = 00h
M6[7:0] = 00h
M7[31:24] = 00h
M7[23:16] = 00h
M7[15:8] = 00h
M7[7:0] = 00h
M8[31:24] = 00h
M8[23:16] = 00h
M8[15:8] = 00h
M8[7:0] = 00h
M9[31:24] = 00h
M9[23:16] = 00h
M9[15:8] = 00h
M9[7:0] = 00h
M10[31:24] = 00h
M10[23:16] = 00h
M10[15:8] = 00h
M10[7:0] = 00h
M11[31:24] = 00h
M11[23:16] = 00h
M11[15:8] = 00h
M11[7:0] = 00h
M12[31:24] = 00h
M12[23:16] = 00h
M12[15:8] = 00h
M12[7:0] = 00h
M13[31:24] = 00h
M13[23:16] = 00h
M13[15:8] = 00h
M13[7:0] = 00h
M14[31:24] = 00h
M14[23:16] = 00h
M14[15:8] = 00h
M14[7:0] = 00h
M15[31:24] = 00h
M15[23:16] = 00h
M15[15:8] = 00h
M15[7:0] = 18h
Mx = Input buffer of SHA-1 engine; 0 ≤ t ≤ 15; 32-bit words with a start address at 00h and ending address at 0Fh.
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