DSSHA1 Datasheet, PDF (4/9 Pages) Maxim Integrated Products – Memory-Mapped SHA-1 Coprocessor Five 32-Bit Registers to Read MAC Result

Memory-Mapped SHA-1 Coprocessor
SHA-1 Engine Control
The DSSHA1 performs the job of a SHA-1 engine. The
input buffer accepts the message. The MAC output
buffer receives the resultant SHA-1 computation. Figure
2 illustrates data flow into and out of the SHA-1 engine.
Applying a power reset initiates the first step of using
the SHA-1 engine. Next, a message is loaded into the
input buffer in the format of Table 1. Upon completion
of a message load, the user pulses the RUN_SHA input
signal. For the duration of the SHA-1 computation, the
BUSY signal goes and remains logic-high. A BUSY sig-
nal goes logic-low again when the SHA-1 computation
completes. All five of the MRR registers (see Table 2)
contain the MAC result for reading.
ACTIVE-LOW RESET
DIRECT READ AND
WRITE ACCESS
64-BYTE
INPUT BUFFER
RUN SHA-1 INPUT PULSE
MAC READ ACCESS (A, B, C, D, AND E)
SHA-1
ENGINE
OUTPUT BUSY SIGNAL DURING CALCULATION
MAC RESULT
20 BYTES
Figure 2. Data Flow Diagram
Table 1. Input Message Format
M0[31:24] = (IB + 0)
M1[31:24] = (IB + 4)
M2[31:24] = (IB + 8)
M3[31:24] = (IB + 12)
M4[31:24] = (IB + 16)
M5[31:24] = (IB + 20)
M6[31:24] = (IB + 24)
M7[31:24] = (IB + 28)
M8[31:24] = (IB + 32)
M9[31:24] = (IB + 36)
M10[31:24] = (IB + 40)
M11[31:24] = (IB + 44)
M12[31:24] = (IB + 48)
M13[31:24] = (IB + 52)
M14[31:24] = (IB + 56)
M15[31:24] = (IB + 60)
M0[23:16] = (IB + 1)
M1[23:16] = (IB + 5)
M2[23:16] = (IB + 9)
M3[23:16] = (IB + 13)
M4[23:16] = (IB + 17)
M5[23:16] = (IB + 21)
M6[23:16] = (IB + 25)
M7[23:16] = (IB + 29)
M8[23:16] = (IB + 33)
M9[23:16] = (IB + 37)
M10[23:16] = (IB + 41)
M11[23:16] = (IB + 45)
M12[23:16] = (IB + 49)
M13[23:16] = (IB + 53)
M14[23:16] = (IB + 57)
M15[23:16] = (IB + 61)
M0[15:8] = (IB + 2)
M1[15:8] = (IB + 6)
M2[15:8] = (IB + 10)
M3[15:8] = (IB + 14)
M4[15:8] = (IB + 18)
M5[15:8] = (IB + 22)
M6[15:8] = (IB + 26)
M7[15:8] = (IB + 30)
M8[15:8] = (IB + 34)
M9[15:8] = (IB + 38)
M10[15:8] = (IB + 42)
M11[15:8] = (IB + 46)
M12[15:8] = (IB + 50)
M13[15:8] = (IB + 54)
M14[15:8] = (IB + 58)
M15[15:8] = (IB + 62)
M0[7:0] = (IB + 3)
M1[7:0] = (IB + 7)
M2[7:0] = (IB + 11)
M3[7:0] = (IB + 15)
M4[7:0] = (IB + 19)
M5[7:0] = (IB + 23)
M6[7:0] = (IB + 27)
M7[7:0] = (IB + 31)
M8[7:0] = (IB + 35)
M9[7:0] = (IB + 39)
M10[7:0] = (IB + 43)
M11[7:0] = (IB + 47)
M12[7:0] = (IB + 51)
M13[7:0] = (IB + 55)
M14[7:0] = (IB + 59)
M15[7:0] = (IB + 63)
Mx = Input buffer of SHA-1 engine; 0 ≤ t ≤ 15; 32-bit words with a start address at 00h and ending address at 0Fh.
IB = Input buffer.
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