DSSHA1 Datasheet, PDF (6/9 Pages) Maxim Integrated Products – Memory-Mapped SHA-1 Coprocessor Five 32-Bit Registers to Read MAC Result

Memory-Mapped SHA-1 Coprocessor
Timing Specification
Figure 3, Figure 4, and Table 4 show delay values mea-
sured from 50% of supply to 50% of supply using an
ARM TSMC CL018G (0.18µm generic process) 1.8V
SAGE-X™ standard cells library, version 2004q3v1, at
+25°C. The output signals are not loaded. Input signals
are driven with a standard slew of 0.200ns from 10% to
90% of supply.
Table 4. Data Bus Interface Timing
PARAMETER
SYMBOL
MIN
MAX
UNITS
CLK Cycle (Note 1)
Chip Select Setup Before Rising Edge of CLK (Note 1)
Chip Select Hold After Rising Edge of CLK (Note 1)
Address and Data Setup Before Rising Edge of CLK (Note 1)
Address and Data Hold After Rising Edge of CLK (Note 1)
Active Output Time to DATAO Valid (Notes 1, 2)
Deactivate DATAO[31:0] (Note 1)
t_CYC
t_CSS
t_CSH
t_AS
t_AH
t_AO
t_D
12.500
ns
0.229
ns
0.000
ns
0.229
ns
0.000
ns
0.984
ns
0.984
ns
Note 1: These values depend upon the process used to realize the circuit. Values shown are for example purposes only and mod-
eled using the ARM TSMC CL018G (0.18µm generic process) 1.8V SAGE-X standard cells library, version 2004q3v1. The
ARM part number is A0082.
Note 2: This time is defined as the longest possible delay to valid output for the typical corners.
CLK
t_CSS
CSZ
ADDR[4:0]
WRZ
DATAI[31:0]
DATAO[31:0]
Figure 3. Write Cycle
t_CYC
t_CSH
t_AS
t_AH
VALID ADDRESS
VALID DATA
t_AO
t_D
VALID DATA
SAGE-X is a trademark of ARM Ltd.
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