DS4830_13 Datasheet, PDF (8/30 Pages) Maxim Integrated Products – Optical Microcontroller

DS4830
Optical Microcontroller
SPI Digital Interface Specification (continued)
(V_DD = 2.97V to 3.63V, T_A = -40NC to +85NC, unless otherwise noted.) (See Figure 3 and Figure 4.)
PARAMETER
SSPIDO Output Valid After
SSPICK Shift Edge Transition
SYMBOL
t_SOV
CONDITIONS
MIN
TYP
MAX UNITS
2t_{SPI_RF} ns
SSPICS Inactive
SSPICK Inactive to SSPICS
Rising
t_SSH
t_SD
t_SSPICK +
t_{SPI_RF}
ns
t_{SPI_RF}
ns
SSPIDO Output Disabled After
SSPICS Edge Rise
t_SLH
2t_SSPICK
+
ns
2t_{SPI_RF}
Electrical Characteristics: JTAG Interface
(V_DD = 2.97V to 3.63V, T_A = -40NC to +85NC, unless otherwise noted.) (Figure 5)
PARAMETER
JTAG Logic Reference
TCK High Time
TCK Low Time
TCK Low to TDO Output
SYMBOL
V_REF
t_TH
t_TL
t_TLQ
CONDITIONS
MIN TYP MAX UNITS
V_DD/2
V
0.5
Fs
0.5
Fs
0.125
Fs
TMS, TDI Input Setup to TCK High t_DVTH
0.25
Fs
TMS, TDI Input Hold After TCK
High
t_THDX
0.25
Fs
Note 1: All voltages are referenced to GND. Currents entering the IC are specified as positive, and currents exiting the IC are
specified as negative.
Note 2: Maximum current assuming 100% CPU duty cycle.
Note 3: This value does not include current in GPIO, SCL, SDA, MDIO, MDI, MCL, REFINA, and REFINB.
Note 4: Using internal reference.
Note 5: There is one internal oscillator. The oscillator (peripheral clock) goes through a 2:1 divider to create the core clock.
Note 6: Guaranteed by design.
Note 7: ADC conversions are delayed up to 1.6Fs if the fast comparator is sampling the selected ADC channel. This can cause a
slight decrease in the ADC sampling rate.
Note 8: Temperature readings average 64 times.
Note 9: Programming time does not include overhead associated with the utility ROM interface.
Note 10: f_SCL must meet the minimum clock low time plus the rise/fall times.
Note 11: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the V_IH:MIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 12: C_B—Total capacitance of one bus line in pF.
Note 13: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Maxim Integrated
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