DS4830_13 Datasheet, PDF (24/30 Pages) Maxim Integrated Products – Optical Microcontroller

DS4830
Optical Microcontroller
Analog-to-Digital Converter
and Sample/Hold
The analog-to-digital converter (ADC) controller is the
digital interface block between the CPU and the ADC. It
provides all the necessary controls to the ADC and the
CPU interface. The ADC uses a set of SFRs for configur-
ing the ADC in desired mode of operation.
The device contains a 13-bit ADC with an input mux
(Figure 9). The mux selects the ADC input from 16 single-
ended or eight differential inputs. Additionally, the chan-
nels can be configured to convert internal and external
temperature, V_DD, internal reference, or REFINA/B. Two
channels can be programmed to be sample/hold inputs.
The internal channel is used exclusively to measure the
die temperature. The SFR registers control the ADC.
ADC
When used in voltage input mode, the voltage applied on
the corresponding channel (differential or single-ended)
is converted to a digital readout. The ADC can be set up
to continuously poll selected input channels (continuous-
sequence mode) or run a short burst of conversions
and enter a shutdown mode to conserve power (single-
sequence mode).
In voltage mode there are four full-scale values that can
be programmed. These values can be trimmed by modi-
fying the associated gain registers (ADCG1, ADCG2,
ADCG3, ADCG4). By default these are set to 1.2V, 0.6V,
2.4V, and 4.8V full scale.
ADCCFG
13-BIT ADC
PGA
ADGAIN
ADC-S[15:0]
ADC-D[7:0][P/N]
ADC-SHP[1:0]
ADC-SHN[1:0]
ADC-REFIN[A/B]
MUX
ADC-VDD
ADC-VREF_2.5V
ADC-TEXT_A(+/-)
ADC-TEXT_B(+/-)
ADC-TINT
ADCONV
(START CONVERSATION)
Figure 9. ADC Block Diagram
The ADCCLK is derived from the system clock with divi-
sion ratio defined by the ADC control register. An A/D
conversion takes 15 ADCCLK cycles to complete with
additional four core clocks used for data processing.
Internally every channel is converted twice and the aver-
age of two conversions is written to the data buffer. This
gives each conversion result in (30 x ADC Clock Period
+ 800ns). ADC sampling rate is approximately 40ksps
for the fastest ADC clock (core clock/8). In applications
where extending the acquisition time is desired, the sam-
ple can be acquired over a prolonged period determined
by the ADC control register.
Each ADC channel can have its own configuration, such
as differential mode select, data alignment select, acqui-
sition extension enable, and ADC gain select, etc. The
ADC also has 24 (0 to 23) 16-bit data buffers for con-
version result storage. The ADC data available interrupt
flag (ADDAI) can be configured to trigger an interrupt
following a predetermined number of samples. Once set,
ADDAI can be cleared by software or at the start of a
conversion process.
Sample/Hold
Pin combinations GP2-GP3 and GP12-GP13 can be
used for sample/hold conversions if enabled in the SHCN
register. These two can be independently enabled or
disabled by writing a 1 or 0 to their corresponding bit
locations in SHCN register. A data buffer location is
reserved for each channel. When a particular channel is
enabled, a sample of the input voltage is taken when a
signal is issued on the SHEN pin, converted and stored
in the corresponding data buffer.
The two sample/hold channels can sample simultane-
ously on the same SHEN signal or different SHEN signals
depending on the SH_DUAL bit in the SHCN SFR.
The sample/hold data available interrupt flag (SHnDAI)
can be configured to trigger an interrupt following sam-
ple completion. Once set, SHnDAI can be cleared by
software.
Each sample/hold circuit consists of a sampling capaci-
tor, charge injection nulling switches, and a buffer.
Also included is a discharge circuit used to discharge
parasitic capacitance on the input node and the sample
capacitor before sampling begins. The negative input
pins can be used to reduce ground offsets and noise.
Maxim Integrated
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