DS4830_13 Datasheet, PDF (26/30 Pages) Maxim Integrated Products – Optical Microcontroller

DS4830
Optical Microcontroller
3) The SCL logic level is high.
4) The I²C-compatible slave interface is disabled.
When a timeout occurs, the timeout bit is set and an inter-
rupt is generated, if enabled.
The I²C master-related SFRs are accessed in module 1.
The I²C slave-related SFRs are accessed in module 2.
Details can be found in the I²C section of the DS4830
User’s Guide.
Serial Peripheral Interface Module
The device supports master and slave SPI interfaces.
The SPI provides an independent serial communication
channel to communicate synchronously with peripheral
devices in a multiple master or multiple slave system. The
interface allows access to a four-wire, full-duplex serial
bus, and can be operated in either master mode or slave
mode. Collision detection is provided when two or more
masters attempt a data transfer at the same time. The
maximum data rate of the SPI is 1/4 the system reference
clock frequency for slave mode and 1/2 the system clock
frequency for master mode.
The four interface signals used by the SPI are as follows:
• Master In-Slave Out. This signal is an output from a
slave device, SSPIDO, and an input to the master
device, MSPIDI. It is used to serially transfer data
from the slave to the master. Data is transferred most
significant bit (MSB) first. The slave device places this
pin in an input state with a weak pullup when it is not
selected.
• Master Out-Slave In. This signal is an output from a
master device, MSPIDO, and an input to the slave
devices, SSPIDI. It is used to serially transfer data
from the master to the slave. Data is transferred MSB
first.
• SPI Clock. This serial clock is an output from the mas-
ter device, MSPICK, and an input to the slave devices,
SSPICK. It is used to synchronize the transfer of data
between the master and the slave on the data bus.
• Active-Low Slave Select. The slave-select signal is
an input to enable the SPI module in slave mode,
SSPICS, by a master device. The SPI module sup-
ports configuration of an active SSPICS state through
the slave-active select. Normally, this signal has no
function in master mode and its port pin can be used
as a general-purpose I/O. However, the SSEL can
optionally be used as a mode fault detection in master
mode.
Maxim Integrated
SPI Master Interface
The master mode is used when the device’s SPI controls
the data transmission rates and data format. The SPI is
placed in master mode by setting the master mode bit
(MSTM). Only an SPI master device can initiate a data
transfer. Writing a data character to the SPI data buffer
(SPIB), when in master mode, starts a data transfer. The
SPI master immediately shifts out the data serially on
MSPIDO, MSB first, while providing the serial clock on
the MSPICK output. New data is simultaneously gated in
on MSPIDI into the least significant bit (LSB) of the shift
register. At the end of a transfer, the received data is
loaded into the data buffer for reading, and the SPI trans-
fer complete flag (SPIC) is set. If SPIC is set, an interrupt
request is generated to the interrupt handler, if enabled.
SPI Slave Interface
Slave mode is used when the SPI is controlled by another
peripheral device. The SPI is in slave mode when an
internal bit (MSTM) is cleared to logic 0. In slave mode
the SPI is dependent on the SSPICK sourced from the
master to control the data transfer. The SSPICK input
frequency should not be greater than the system clock
frequency of the slave device divided by 4. The SPI mas-
ter transfers data to a slave on SSPIDI, MSB first, and
the selected slave device simultaneously transfers the
contents of its shift register to the master on SSPIDO, also
MSB first. Data received from the master replaces data
in the slave’s shift register at the completion of a transfer.
Just like in the master mode, received data is loaded into
the read buffer, and the SPI transfer complete flag is set
at the end of the transfer. The setting of the transfer com-
plete flag can cause an interrupt if enabled.
The SPI master-related SFRs are accessed in module 5.
The SPI slave-related SFRs are accessed in module 1.
Details can be found in the SPI section of the DS4830
User’s Guide.
3-Wire Interface Module
The DS4830 controls devices like the MAX3798/MAX3799
over a proprietary 3-wire interface. The DS4830 acts as
the 3-wire master, initiating communication with and
generating the clock for the MAX3798/MAX3799. It is a
3-pin interface consisting of MDIO (a bidirectional data
line), an MCL clock signal, and a MCS chip-select output
(active high).
The 3-wire master-related SFRs are accessed in mod-
ule 2. Detailed information regarding the 3-wire interface
block can be found in the DS4830 User’s Guide.
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