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MAX11301 Datasheet, PDF (7/55 Pages) Maxim Integrated Products – Programmable Sample Averaging Per ADC Port
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
DAC Electrical Specifications (continued)
(VAVDD = 4.75V to 5.25V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V
(Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
TRACK-AND-HOLD
Digital Feedthrough
5
nV·s
Hold Step
(Note 6)
1
6
mV
Droop Rate
(Note 6)
0.3
15
mV/s
Interface Digital IO Electrical Specifications
(VAVDD = 5.0V, VDVDD = 1.62V to 5.50V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V
(Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
I2C IO DC SPECIFICATION
Input Logic-High Voltage
(SDA, SCL, AD0, AD1, CNVT)
VDVDD = 2.5V to 5.5V
VDVDD = 1.62V to 2.5V
0.7 x
VDVDD
0.85 x
VDVDD
V
Input Logic-Low Voltage
(SDA, SCL, AD0, AD1, CNVT)
VDVDD = 2.5V to 5.5V
VDVDD = 1.62V to 2.5V
0.3 x
VDVDD
V
0.15 x
VDVDD
Input Leakage Current
(SDA, SCL, AD0, AD1, CNVT)
-10
+10
µA
Input Capacitance
(SDA, SCL, AD0, AD1, CNVT)
10
pF
Output Logic-Low Voltage (SDA)
ISNK = 3mA
0.4
V
Output Logic-Low Voltage (INT)
ISNK = 5mA, VDVDD = 2.5V to 5.5V
ISNK = 2mA, VDVDD = 1.62V to 2.5V
0.4
V
0.2
I2C TIMING REQUIREMENTS (Fast Mode) (See Figure 1)
Serial Clock Frequency
fSCL
Bus Free Time Between STOP
and START Condition
tBUF
0
400
kHz
1.3
µs
Hold Time (Repeated) START
Condition
tHD;STA
After this period, first clock pulse is
generated
0.6
µs
SCL Pulse-Width Low
SCL Pulse-Width High
tLOW
tHIGH
1.3
µs
0.6
µs
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