MAX11301 Datasheet, PDF (31/55 Pages) Maxim Integrated Products – Programmable Sample Averaging Per ADC Port

MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Interrupt Operations
The MAX11301 issues interrupts to alert the host of vari-
ous events. All events are recorded by the interrupt reg-
ister. The assertion of an interrupt register bit results in
the assertion of the interrupt port (INT) if that interrupt bit
is not masked. By default, all interrupts are masked upon
power-up or reset. The interrupts are listed hereafter.
The ADCFLAG (ADC Flag) interrupt indicates that the
ADC just completed a conversion or set of conversions.
It is asserted either at the end of a conversion when the
ADC is in single-conversion mode or at the end of a
sweep when the ADC is either in single-sweep mode or
continuous-sweep mode. ADCFLAG is cleared when the
interrupt register is read.
The ADCDR (ADC Data Ready) interrupt is asserted
when at least one ADC data register is refreshed. Since
one conversion per ADC-configured port is performed per
sweep, many sweeps may be required before refresh-
ing the data register of a given ADC-configured port that
utilizes the averaging function. (See the ADC Averaging
Function section) To determine which ADC-configured
port received a new data sample, the host must read
the ADC status registers. ADCDR is cleared after the
interrupt register and both ADC status registers are read
subsequently.
The ADCDM (ADC Data Missed) interrupt is asserted when
any ADC data register is not read by the host before new
data is stored in that ADC data register. ADCDM is cleared
after the interrupt register is read.
The GPIER (GPI Event Received) interrupt indicates that
an event has been received on one of the GPI-configured
ports. Each GPI port can be configured to generate an
interrupt for an event such as detecting a rising edge, a
falling edge, or either edge at the corresponding port. If
the GPI port is configured to detect no edge, it is equiva-
lent to masking the interrupt related to that port. A GPI sta-
tus register allows the host to identify which port detected
the event. GPIER is cleared after the interrupt register
and both GPI status registers are read subsequently.
The GPIEM (GPI Event Missed) interrupt informs the
host that it did not service the GPI interrupt caused by the
occurrence of an event recorded by GPI status registers
before another event was received on the same port. The
host must read the interrupt register and the GPI status
registers whenever a GPI event received interrupt occurs;
otherwise, the GPIEM register is asserted upon receiving
the next event. This interrupt must be used in conjunction
with the GPIER interrupt bit to operate properly. GPIEM
is cleared after the interrupt register and both GPI status
registers are read subsequently.
The DACOI (DAC Overcurrent) interrupt indicates that
a DAC-configured port current exceeded approximately
50mA. This limit is not configurable. A DAC overcurrent
status register allows the host to identify which DAC-
configured port exceeded the 50mA current limit. DACOI
is cleared after the interrupt register is read, and both
DAC overcurrent status registers are read subsequently.
The TMPINT[2:0] (Internal Temperature Monitor) inter-
rupt has three sources of interrupt, each independently
controllable: a new internal temperature data is ready, the
internal temperature value exceeds the maximum limit, or
the internal temperature value is below the minimum limit.
TMPINT is cleared after the interrupt register is read.
The TMPEXT1[2:0] (1st External Temperature Monitor)
interrupt has three sources of interrupt, each indepen-
dently controllable: a new first external temperature data
is ready, the first external temperature value exceeds the
maximum limit, or the first external temperature value is
below the minimum limit. TMPEXT1 is cleared after the
interrupt register is read.
The TMPEXT2[2:0] (2nd External Temperature Monitor)
interrupt has three sources of interrupt, each indepen-
dently controllable: a new second external temperature
data is ready, the second external temperature value
exceeds the maximum limit, or the second external tem-
perature value is below the minimum limit. TMPEXT2 is
cleared after the interrupt register is read.
The VMON (High-Voltage Supply Monitor) Supply Voltage
Failure) interrupt is triggered when AVDDIO supply voltage
falls below 4V, approximately. VMON is cleared after the
interrupt register is read.
PIXI PORT[i]
Figure 11. PIXI Ports as a Controllable Analog Switch
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GPI ANY OTHER PORT
PIXI PORT[i+1]
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