MAX11301 Datasheet, PDF (25/55 Pages) Maxim Integrated Products – Programmable Sample Averaging Per ADC Port

MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
ANY
PORT
ANY OTHER
PORT
SCALING
BLOCK
SCALING
BLOCK
ADC_INT_REF ADC_EXT_REF
SEQUENCER
REFERENCE
MUX
ADC
DIGITAL
CORE
CNVT
I²C
SERIAL
INTERFACE
INT
SCALING
BLOCK
DAC_REF
INTERNAL OR
EXTERNAL FOR
ALL PORTS
SEQUENCER
DAC
Figure 4. ADC with Pseudo-Differential Input Set by DAC
SERIAL
INTERFACE
I²C
DAC_REF
INTERNAL OR
EXTERNAL FOR
ALL PORTS
DIGITAL
CORE
DAC
40µs to ±1 LSB
SEQUENCER
SCALING
BLOCK
PORT
0mA → 25mA
CURRENT LIMIT at
50mA
INT
Figure 5. DAC Configuration
General-Purpose Input and Output
Each PIXI port can be configured as a GPI or a GPO. The
GPI threshold is adjusted by setting the DAC data register
of that GPI port to the corresponding voltage. If the DAC
data register is set at 0x0FFF, the GPI threshold is the DAC
reference voltage. The amplitude of the input signal must
be contained within 0V to V_AVDD. The GPI-configured port
can be set to detect rising edges, falling edges, either rising
or falling edges, or none.
When a port is configured as GPO (Figure 8), the ampli-
tude of its logic-one level is set by its DAC data register. If
the DAC data register is set at 0x0FFF, the GPO logic-one
level is four times the DAC reference voltage. The logic-
zero level is always 0V. The host can set the logic state
of GPO-configured ports through the corresponding GPO
data registers.
Unidirectional and Bidirectional
Level Translator Operations
By combining GPI- and GPO-configured ports, unidirec-
tional level translator paths can be formed. The signaling
at the input of the path can be different from the signaling
at the end (Figure 9). For example, a unidirectional path
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