MAX11301 Datasheet, PDF (26/55 Pages) Maxim Integrated Products – Programmable Sample Averaging Per ADC Port

MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
SERIAL
INTERFACE
I²C
DAC_REF
INTERNAL OR EXTERNAL
FOR ALL PORTS
DIGITAL
CORE
DAC
SEQUENCER
CNVT
SCALING
BLOCK
PORT
ADC_INT_REF DAC_REF
REFERENCE
MUX
ADC
SCALING
BLOCK
SEQUENCER
INT
Figure 6. DAC Configuration with ADC Monitoring
could convert a signal from 1.8V logic level to 3.3V logic
level.
The unidirectional path configuration allows for the trans-
mission of signals received on a GPI-configured port to
one or more GPO-configured ports.
Pairs of adjacent PIXI ports can also form bidirectional
level translator paths that are targeted to operate with
open-drain drivers (Figure 10). When used as a bidi-
rectional level translator, the pair of PIXI ports must be
accompanied with external pullup resistors to meet proper
logic levels.
Internally or Externally Controlled
Analog Switch Operation
Two adjacent PIXI ports can form a 60Ω analog switch
that is controlled by two different configurations. In one
configuration, the switch is dynamically controlled by any
other GPI-configured PIXI port, as illustrated in Figure
11. The signal applied to that GPI-configured port can be
inverted.
In the other configuration, the switch is programmed to be
permanently “ON” by configuring the corresponding PIXI
port. To turn the switch “OFF”, the host must set that PIXI
port in high-impedance configuration.
Power-Supply Brownout Detection
The MAX11301 features a brownout detection circuit that
monitors AVDDIO and AVDD pins. When AVDDIO goes
below approximately 4.0V, an interrupt is registered, and
the interrupt port is asserted if not masked. When AVDD
goes below approximately 4.0V, the device resets.
I²C Operations
The MAX11301 serial interface is compatible with the I²C
Fast Mode (SCL at 400kHz).
The MAX11301 has a configurable 7-bit slave address.
The first four bits of all MAX11301 slave addresses are
always 0111. Slave address bits A2, A1, and A0 are
shown in Table 1. The AD0 and AD1 inputs are connected
to any of three signals: DGND, DVDD, SDA, or SCL giving
eight possible slave addresses, and allowing up to eight
MAX11301 devices to share the bus.
Basic write and read transactions are structured as shown
in Table 2 and Table 3, respectively. For write transac-
tions, the targeted register content is modified only after
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