DS4M125 Datasheet, PDF (6/7 Pages) Maxim Integrated Products – 3.3V Margining Clock Oscillator with LVPECL/LVDS Output

3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
VCC
X1
X2
DS4M125/
DS4M133/
DS4M200
THREE-
MS
LEVEL
DECODER
THREE-
LC-VCO
STATE
PHASE
FILTER
DIVP
DET
DIVFB
DIVOUT
OUTSELN
OUTDRV
OE
OUTP
OUTN
FREQUENCY SELECTION
GND
Figure 1. Functional Diagram
Detailed Description
The DS4M125/DS4M133/DS4M200 consist of an oscil-
lator designed to oscillate with a fundamental-mode
crystal and a PLL to synthesize the base frequency with
its ±5% deviations. The output interface is either
LVPECL or LVDS.
The ±5% frequency deviation is controlled through a
three-level margining select (MS) pin. This three-state
input pin accepts a three-level voltage signal to control
the output frequency. In a low-level state, the output
frequency is set to the nominal frequency. When set to
a high-level state, the frequency output is set to the
nominal frequency plus 5%. When set to the mid-level
state, the frequency output is equal to the nominal fre-
quency minus 5%. The MS pin has an internal 100kΩ
pulldown resistor. When the pin is left floating, the
devices output a nominal frequency.
The devices are available with either LVDS or LVPECL
output drivers. When the OE signal is low, the LVPECL
output driver is turned off and the output voltage goes
to the PECL_BIAS level of V_CC - 2.0V, while the LVDS
outputs are a logical one. The OE pin has an internal
100kΩ pullup resistor. When the pin is left floating, the
device output is active.
0.7 x V_CC
OE
t_P1A
OUTP
0.3 x V_CC
t_PA1
0.7 x V_CC
OE
t_PZA
PECL_BIAS
OUTP
0.3 x V_CC
t_PAZ
PECL_BIAS
OUTN
PECL_BIAS
OUTN
PECL_BIAS
Figure 2. LVDS Output Timing Diagram When OE Is Enabled
and Disabled
Figure 3. LVPECL Output Timing Diagram When OE Is Enabled
and Disabled
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