DS4M125 Datasheet, PDF (4/7 Pages) Maxim Integrated Products – 3.3V Margining Clock Oscillator with LVPECL/LVDS Output

3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
ELECTRICAL CHARACTERISTICS (continued)
(V_CC = 3.135V to 3.465V, T_A = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER
LVPECL
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output High Voltage (Note 2)
V_OH
Output connected to 50 at PECL_BIAS V_CC -
at V_CC - 2.0V
1.085
V_CC -
V
0.88
Output Low Voltage (Note 2)
V_OL
Output connected to 50 at PECL_BIAS V_CC -
at V_CC - 2.0V
1.825
V_CC -
1.62
V
Differential Voltage
V_{DIFF_PECL}
Output connected to 50 at PECL_BIAS
at V_CC - 2.0V
0.595
0.710
V
Rise Time
Fall Time
t_R-PECL
t_F-PECL
20% to 80%
80% to 20%
200
ps
200
ps
Duty Cycle
D_{CYCLE_PECL}
45
55
%
Propagation Delay from OE Going
LOW to Output Three-Stated
t_PAZ
(Figure 3)
200
ns
Propagation Delay from OE Going
HIGH to Output Active
t_PZA
(Figure 3)
200
ns
Note 1: Limits at -40°C are guaranteed by design and are not production tested. Typical values are at +25°C and 3.3V, unless
otherwise noted.
Note 2: AC parameters are guaranteed by design and characterization and are not production tested.
Note 3: Frequency stability is calculated as: Δf_TOTAL = Δf_INITIAL + Δf_TEMP + (Δf_VCC x 0.165) + Δf_LOAD + Δf_AGING.
Note 4: Supply induced jitter is measured with a 50mV_P-P sine wave forced on V_CC. Deterministic jitter is calculated by measuring
the power of the resulting tone seen on a spectrum analyzer.
Note 5: Voltage referenced to ground.
SINGLE-SIDEBAND PHASE NOISE AT f_O = f_NOM
f_M =
10H z
100Hz
1kHz
10kHz
100 kH z
1MHz
10MH z
20MH z
SINGLE-SIDEBAND PHASE NOISE AT f_O = f_NOM (dBc/Hz)
125MHz
133.33MHz
200MHz
-70
-75
-70
-100
-105
-100
-118
-121
-115
-118
-122
-117
-124
-126
-122
-142
-141
-138
-150
-150
-150
-150
-150
-150
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