DS4M125 Datasheet, PDF (1/7 Pages) Maxim Integrated Products – 3.3V Margining Clock Oscillator with LVPECL/LVDS Output

Rev 0; 12/07
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
General Description
The DS4M125/DS4M133/DS4M200 are margining clock
oscillators with LVPECL or LVDS outputs. They are
designed to fit in a 5mm x 3.2mm ceramic package with
an AT-cut fundamental-mode crystal to form a complete
clock oscillator. The circuit can generate the following
frequencies and their ±5% frequency deviations:
125MHz, 133.33MHz, and 200MHz. The DS4M125/
DS4M133/DS4M200 employ a low-jitter PLL to generate
the frequencies. The typical phase jitter is less than
0.9ps RMS from 12kHz to 20MHz.
Frequency margining is a circuit operation to change
the output frequency to 5% higher or 5% lower than the
nominal frequency. Frequency margining is accom-
plished through the margining select pin, MS. This
three-state input pin accepts a three-level voltage signal
to control the output frequency. In a low-level state, the
output frequency is set to the nominal frequency. When
set to a high-level state, the frequency output is set to
the nominal frequency plus 5%. When set to the mid-
level state, the frequency output is equal to the nominal
frequency minus 5%. If left open, the MS pin is pulled
low by an internal 100kΩ (nominal) pulldown resistor.
The DS4M125/DS4M133/DS4M200 are available with
either an LVPECL or LVDS output. The output can be
disabled by pulling the OE pin low. When disabled,
both OUTP and OUTN levels of the LVPECL driver go to
the LVPECL bias voltage, while the output of the LVDS
driver is a logical one. The OE input is an active-high
logic signal and has an internal 100kΩ pullup resistor.
When OE is in a logic-high state, the OUTP and OUTN
outputs are enabled.
The devices operate from a single 3.3V supply voltage.
Memory Clocks
RAID Systems
Applications
Features
♦ Frequency Margining: ±5%
♦ Nominal Clock Output Frequencies: 125MHz,
133.33MHz, and 200MHz
♦ Jitter < 0.9ps RMS from 12kHz to 20MHz
♦ LVPECL or LVDS Output
♦ 3.3V Operating Voltage
♦ Operating Temperature Range: -40°C to +85°C
♦ Supply Current: < 100mA at 3.3V
♦ Excellent Power-Supply Noise Rejection
♦ 5mm x 3.2mm Ceramic LCCC Package
♦ Output Enable/Disable
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
DS4M125P+33 -40°C to +85°C 10 LCCC
DS4M125D+33 -40°C to +85°C 10 LCCC
DS4M133P+33 -40°C to +85°C 10 LCCC
DS4M133D+33 -40°C to +85°C 10 LCCC
DS4M200P+33 -40°C to +85°C 10 LCCC
DS4M200D+33 -40°C to +85°C 10 LCCC
+Denotes a lead(Pb)-free package. The lead finish is JESD97
category e4 (Au over Ni) and is compatible with both lead-based
and lead-free soldering processes.
Pin Configuration and Selector Guide appear at end of
data sheet.
Typical Operating Circuit
0.1μF
0.01μF
VCC
OUTP
DS4M125/
MS _DS4M133/
OE ^DS4M200
GND
OUTN
LVDS OPTION
100Ω
0.1μF
0.01μF
VCC
OUTP
DS4M125/
MS _DS4M133/
OE ^DS4M200
GND
OUTN
LVPECL OPTION
50Ω
PECL_BIAS AT
V_CC - 2.0V
50Ω
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