MAX11358B Datasheet, PDF (55/70 Pages) Maxim Integrated Products – 16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor

16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
SW_CTRL Register (Power-On State: 0000 00XX)
MSB
SWA
SWB
SPDT11
SPDT10
The switch-control register controls the two SPDT
switches (SPDT1 and SPDT2) and the DACA output
buffer SPST switch (SWA). Control this switch by the
serial bits in this register, by any of the UPIO pins that
are enabled for that function, or by the PWM.
SWA: DACA output buffer SPST-switch A control bit.
The SWA bit, the UPIO inputs (if configured), and the
PWM (if configured) control the state of the SWA switch
as shown in Table 17. The UPIO_ states of 0 and 1 in the
table correspond to respective deasserted and asserted
logic states as defined by the ALH_ bit of the
UPIO_CTRL register. If a UPIO is not configured for this
mode, its value applied to the table is 0. The PWM
states of 0 and 1 in the table correspond to the respec-
tive PWM off (or low) and on (or high) states defined by
the SWAH and SWAL bits (see the PWM_CTRL Register
section). If the PWM is not configured for this mode, its
value applied to the table is 0. The power-on default is 0.
SWB: DACB output buffer SPST-switch B control bit.
The SWB bit, the UPIO inputs (if configured), and the
PWM (if configured) control the state of the SWB switch
as shown in Table 18. The UPIO_ states of 0 and 1 in the
table correspond to respective deasserted and asserted
logic states as defined by the ALH_ bit (see the
UPIO_CTRL Register section). If a UPIO is not config-
ured for this mode, its value applied to the table is 0.
The PWM states of 0 and 1 in the table correspond to
the respective PWM off (or low) and on (or high) states
defined by the SWBH and SWBL bits (see the
PWM_CTRL Register section). If the PWM is not config-
ured for this mode, its value applied to the table is 0.
The power-on default is 0.
SPDT1<1:0>: Single-pole double-throw switch 1 con-
trol bits. The SPDT1<1:0> bits, the UPIO pins (if config-
ured), and the PWM (if configured) control the state of
the switch as shown in Table 18. The UPIO_ states of 0
and 1 in the table correspond to respective deasserted
and asserted logic states as defined by the ALH_ bit of
the UPIO_CTRL register. If a UPIO is not configured for
this mode, its value applied to Table 18 is 0. The PWM
states of 0 and 1 in Table 18 correspond to the respec-
tive PWM off (low) and on (high) states defined by the
SPD1 bit in the PWM_CTRL register. If the PWM is not
configured for this mode, its value applied to Table 18
is 0. The power-on default is 00.
SPDT21
SPDT20
X
LSB
X
Table 17. SWA States
SW_ BIT* UPIO_*
PWM* SW_ SWITCH STATE
0
0
0
Switch open
X
X
1
Switch closed
X
1
X
Switch closed
1
X
X
Switch closed
X = Don’t care.
*Switch SW_ control is effectively an OR of the SW_ bit, UPIO_
pins, and PWM.
Table 18. SPDT Switch 1 States
SPDT1<1:0>
0
0
0
X
0
X
0
1
1
0
1
X
1
X
1
1
UPIO_*
0
X
1
X
0
X
1
X
PWM*
0
1
X
X
0
1
X
X
SPDT1 SWITCH STATE
SNO1 open, SNC1 open
SNO1 closed, SNC1 closed
SNO1 closed, SNC1 closed
SNO1 closed, SNC1 closed
SNC1 closed, SNO1 open
SNC1 open, SNO1 closed
SNC1 open, SNO1 closed
SNC1 open, SNO1 closed
X = Don’t care.
*Switch SPDT1 control is effectively an OR of the SPDT10 bit, the
UPIO_ pins, and the PWM output. The SPDT11 bit determines if
the switches open and close together or if they toggle.
Table 19. SPDT Switch 2 States
SPDT2<1:0> UPIO_* PWM* SPDT2 SWITCH STATE
0
0
0
0 SNO2 open, SNC2 open
0
X
X
1 SNO2 closed, SNC2 closed
0
X
1
X SNO2 closed, SNC2 closed
0
1
X
X SNO2 closed, SNC2 closed
1
0
0
0 SNC2 closed, SNO2 open
1
X
X
1 SNC2 open, SNO2 closed
1
X
1
X SNC2 open, SNO2 closed
1
1
X
X SNC2 open, SNO2 closed
X = Don’t care.
*Switch SPDT2 control is effectively an OR of the SPDT20 bit, the
UPIO_ pins, and the PWM output. The SPDT21 bit determines if
the switches open and close together or if they toggle.
______________________________________________________________________________________ 55