MAX11358B Datasheet, PDF (12/70 Pages) Maxim Integrated Products – 16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor

16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
TIMING CHARACTERISTICS (Figures 1 and 19)
(AV_DD = DV_DD = +1.8V to +3.6V, external V_REF = +1.25V, CLK32K = 32.768kHz (external clock), C_REG = 10µF, C_CPOUT = 10µF,
10µF between CF+ and CF-, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SCLK Operating Frequency
SCLK Cycle Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
f_SCLK
t_CYC
t_CH
t_CL
t_DS
t_DH
t_DO
t_DV
t_TR
t_CSS
t_CSH
C_L = 50pF, Figure 2
C_L = 50pF, Figure 2
C_L = 50pF, Figure 2
0
10
MHz
100
ns
40
ns
40
ns
30
ns
0
ns
40
ns
48
ns
48
ns
20
ns
0
ns
DV_DD Monitor Timeout Period
t_DSLP (Note 16)
1.5
s
Wake-Up (WU) Pulse Width
t_WU
Minimum pulse width required to detect a
wake-up event
1
μs
Shutdown Delay
t_DPU
The delay for SHDN to go high after a valid
wake-up event
1
μs
HFCLK Turn-On Time
t_DFON
The turn-on time for the high-frequency
clock and FLL (FLLE = 1) (Note 17)
If FLLE = 0, the turn-on time for the high-
frequency clock (Note 18)
10
ms
10
μs
CRDY to INT Delay
The delay for CRDY to go low after the
t_DFI
HFCLK clock output has been enabled
(Note 19)
7.82
ms
HFCLK Disable Delay
The delay after a shutdown command has
t_DFOF asserted and before HFCLK is disabled
1.95
ms
(Note 20)
SHDN Assertion Delay
t_DPD (Note 21)
2.93
ms
Note 16: The delay for the sleep voltage monitor output, RESET, to go high after V_DD rises above the reset threshold. This is largely
driven by the startup of the 32kHz oscillator.
Note 17: FLLE is gated by an AND function with three inputs—the external RESET signal, the internal DV_DD monitor output, and the
external SHDN signal. The time delay is timed from the internal LOV_DD going high or the external RESET going high,
whichever happens later. HFCLK always starts in the low state.
Note 18: If FLLE = 0, the internal signal CRDY is not generated by the FLL block and INT or INT is deasserted.
Note 19: CRDY is used as an interrupt signal to inform the µC that the high-frequency clock has started. Only valid if FLLE = 1.
Note 20: t_DFOF gives the µC time to clean up and go into sleep-override mode properly.
Note 21: t_DPD is greater than the HFCLK delay to clean up before losing power.
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