MAX11358B Datasheet, PDF (31/70 Pages) Maxim Integrated Products – 16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor

16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Watchdog
Enable the watchdog timer by writing a 1 to the WDE
bit in the CLK_CTRL register. After enabling the watch-
dog timer, the device asserts RESET for 250ms, if the
watchdog address register is not written every 500ms.
Due to the asynchronous nature of the watchdog timer,
the watchdog timeout period varies between 500ms
and 750ms. Write a 0 to the WDE bit to disable the
watchdog timer. See Figure 11 for a block diagram of
the watchdog timer.
High-Frequency Clock
An internal oscillator and an FLL are used to generate a
4.9152MHz ±1% high-frequency clock. This clock and
derivatives are used internally by the ADC, analog
switches, and PWM. This clock signal outputs to CLK.
When the FLL is enabled, the high- frequency clock is
locked to the 32.768kHz reference. If the FLL is dis-
abled, the high-frequency clock is free-running. At
power-up, the CLK pin defaults to a 2.4576MHz clock
output, which is compatible with most µCs. See Figure
12 for a block diagram of the high-frequency clock.
User-Programmable I/Os
The MAX11358B provides four digital programmable
I/Os (UPIO1–UPIO4). Configure UPIOs as logic inputs
or outputs using the UPIO control register. Configure
the internal pullups using the UPIO setup register, if
required. At power-up, the UPIOs are internally pulled
up to DV_DD. UPIO_ outputs can be referenced to DV_DD
or CPOUT. See the UPIO__CTRL Register and
UPIO_SPI Register sections for more details on config-
uring the UPIO_ pins.
32KOUT
32KIN
OSCE
32kHz
OSCILLATOR
32K
32.768kHz OSCILLATOR
Figure 9. 32kHz Crystal-Oscillator Block Diagram
32K
CLK32K
OSCE
CK32E
IO32E
IO32E
IO32E
0
2:1
MUX
1
CLK32K I/O CONTROL
M32K
Figure 10. CLK32K I/O Block Diagram
POR PULSES HIGH DURING POWER-UP.
WDW PULSES HIGH DURING WATCHDOG REGISTER WRITE.
32K
WDE
D
Q
DIVIDE-
BY-8192
4Hz
CK Q
R
DQ
CK _Q
R
WDTO
POR
WDW
WATCHDOG TIMER
Figure 11. Watchdog Timer Block Diagram
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