MAX11358B Datasheet, PDF (38/70 Pages) Maxim Integrated Products – 16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor

16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Table 6a. Setting the ADC Conversion Rate*
CONTINUOUS SINGLE
CONVERSION CONVERSION RATE2
RATE (sps) RATE (sps)
10
2.5
0
40
10
0
50
12.5
0
60
15
0
200
50
1
240
60
1
400
100
1
477
128
1
RATE1
0
0
1
1
0
0
1
1
RATE0
0
1
0
1
0
1
0
1
Table 6b. Actual ADC Conversion Rates
NOMINAL
CONTINUOUS
CONVERSION
RATE (sps)
DECIMATION
RATIO
ACTUAL
CONTINUOUS
CONVERSION
RATE (sps)
10
1096
10.01
40
274
40.04
50
220
49.87
60
183
59.95
200
55
199.48
240
46
238.51
400
27
406.35
477
23
477.02
*Calculate the ADC sampling rate using the following
equation:
f_S
=
448
×
f_HFCLK
decimation
ratio
where f_HFCLK = 4.9152MHz nominally.
RATE<2:0>: ADC conversion-rate-setting bits. These
three bits set the conversion rate of the ADC as shown
in Table 6. The initial conversion requires four conver-
sion cycles for valid data, and subsequent conversions
require only one cycle (if CONT = 1). A full-scale input
change can require up to five cycles for valid data if
the digital filter is not reset with the STRT or S bit.
MODE<2:0>: Conversion-mode bits. These three bits
determine the type of conversion for the ADC as shown
in Table 7. When the ADC finishes an offset calibration
and/or gain calibration, the MODE<2:0> bits clear to 0
hex, the ADD bit in the STATUS register asserts, and
an interrupt asserts on INT (or UPIO_ if programmed as
DRDY) if MADD is unmasked. Perform a gain calibra-
tion after achieving the desired offset (calibrated or
not). If an offset and gain calibration are performed
together (MODE<2:0> = 7 hex), the offset calibration is
performed first followed by the gain calibration, and the
µC is interrupted by INT (or UPIO_ if programmed as
DRDY) if MADD is unmasked only upon completion of
both offset and gain calibration. After power-on or cali-
bration, the ADC does not begin conversions until initi-
ated by the user (see the ADCE and STRT bit
descriptions in this section and see the S bit descrip-
tions in the MUX Register section). See the GAIN CAL
Register and OFFSET CAL Register sections for details
on system calibration.
Table 7. Setting the ADC Conversion Mode
CONVERSION MODE
Normal
System Offset Calibration
System Gain Calibration
Normal
Normal
Self-Offset Calibration
Self-Gain Calibration
MODE2
0
0
0
0
1
1
1
MODE1
0
0
1
1
0
0
1
MODE0
0
1
0
1
0
1
0
Self-Offset and Gain
Calibration
1
1
1
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