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MAX11358B Datasheet, PDF (29/70 Pages) Maxim Integrated Products – 16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
DVDD
1.22V
LDOE
OP
1.65V
REG
M32K
REG
CPE
NONOVERLAP
CLOCK GENERATOR
CPOUT
CF+
CF-
LDOE
LINEAR 1.65V VOLTAGE REGULATOR
Figure 5. Linear-Regulator Block Diagram
CHARGE-PUMP DOUBLER
Figure 6. Charge-Pump Block Diagram
Voltage Supervisors
The MAX11358B provides voltage supervisors to monitor
DVDD and CPOUT. The first supervisor monitors the
DVDD supply voltage. RESET asserts and sets the corre-
sponding LDVD status bit when DVDD falls below the
1.8V threshold voltage. When the DVDD supply voltage
rises above the threshold during power-up, RESET
deasserts after a nominal 1.5s timeout period to give the
crystal oscillator time to stabilize. Set the threshold hys-
teresis using the HYSE bit of the PS_VMONS register.
See the PS_VMONS Register section for configuring hys-
teresis. There is no separate voltage monitor for AVDD,
but the analog supply is covered by the DVDD monitor in
many applications where DVDD and AVDD are externally
connected together. Multiple supply applications where
AVDD and DVDD are not connected together require a
separate external voltage monitor for AVDD. See Figure 7
for a block diagram of the DVDD voltage supervisor.
The second voltage monitor tracks the charge-pump
output voltage, CPOUT. If CPOUT falls below the 2.7V
threshold, a corresponding register status bit (LCPD) is
set to flag the condition. The CPOUT monitor output
can also be mapped to the interrupt generator and out-
put on INT. The CPOUT monitor can be used as a 3V
AVDD monitor in applications where the charge pump is
disabled and CPOUT is connected to AVDD. AVDD
must be greater or equal to DVDD when CPOUT is used
to monitor AVDD. See Figure 8 for a block diagram of the
CPOUT voltage supervisor.
Interrupt Generator (INT)
The interrupt generator provides an interrupt to an
external µC. The source of the interrupt is generated by
the status register and can be masked and unmasked
through the IMSK register. CRDY is unmasked by
default, and INT is active-high at power-on reset. INT is
programmable as active-high and active-low. Possible
sources include a rising or falling edge of UPIO_, an
RTC alarm, an ADC conversion completion, or the volt-
age-supervisor outputs. The interrupt causes INT to
assert when configured as an interrupt output.
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