MAX1191 Datasheet, PDF (5/27 Pages) Maxim Integrated Products – Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = 3.0V, OV_DD = 1.8V, V_REFIN = V_DD (internal reference), C_L ≈ 10pF at digital outputs, f_CLK = 7.5MHz, C_REFP = C_REFN = C_COM
= 0.33µF, T_A = -40°C to +85°C, unless otherwise noted. Typical values are at T_A = +25°C.) (Note 1)
PARAMETER
Analog Supply Current
SYMBOL
CONDITIONS
MIN
Normal operating mode, f_IN = 1.875MHz
at -0.5dB FS, CLK input from GND to V_DD
Idle mode (tri-state), f_IN = 1.875MHz at -
0.5dB FS, CLK input from GND to V_DD
I_DD
Standby mode, CLK input from GND to
V_DD
Shutdown mode, CLK = GND or V_DD,
PD0 = PD1 = OGND
TYP
4.0
4.0
2.2
0.1
MAX
5.0
UNITS
mA
5.0
µA
Normal operating mode,
f_IN = 1.875MHz at -0.5dB FS, C_L ≈ 10pF
Digital Output Supply Current
(Note 3)
I_ODD
Idle mode (tri-state), DC input, CLK =
GND or V_DD, PD0 = OV_DD, PD1 = OGND
Standby mode, DC input, CLK = GND or
V_DD, PD0 = OGND, PD1 = OV_DD
Shutdown mode, CLK = GND or V_DD,
PD0 = PD1 = OGND
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
t_DOA
50% of CLK to 50% of data, Figure 5
(Note 4)
1
1.0
mA
0.1
5.0
0.1
µA
0.1
5.0
6
8.5
ns
CLK Fall to CHB Output Data
Valid
CLK Rise/Fall to A/B Rise/Fall
Time
PD1 Rise to Output Enable
PD1 Fall to Output Disable
CLK Duty Cycle
CLK Duty-Cycle Variation
t_DOB
t_DA/B
t_EN
t_DIS
50% of CLK to 50% of data, Figure 5
(Note 4)
50% of CLK to 50% of A/B, Figure 5
(Note 4)
PD0 = OV_DD
PD0 = OV_DD
1
6
8.5
ns
1
6
8.5
ns
5
ns
5
ns
50
%
±10
%
Wake-Up Time from Shutdown
Mode
t_{WAKE, SD} (Note 5)
20
µs
Wake-Up Time from Standby
Mode
t_{WAKE, ST} (Note 5)
Digital Output Rise/Fall Time
20% to 80%
INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
Amplitude Matching
Phase Matching
f_IN,X = 1.875MHz at -0.5dB FS,
f_IN,Y = 0.3MHz at -0.5dB FS (Note 6)
f_IN = 1.875MHz at -0.5dB FS (Note 7)
f_IN = 1.875MHz at -0.5dB FS (Note 7)
5.5
2
-75
±0.03
±0.03
µs
ns
dB
dB
Degrees
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