MAX1191 Datasheet, PDF (19/27 Pages) Maxim Integrated Products – Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
V_COM = 0.5V TO 1.5V
V_SIG = ±85mV_P-P
R1
600Ω
R2
300Ω
R3
600Ω
R4
600Ω
R5
600Ω
R6
600Ω
R8
600Ω
R7
600Ω
R9
600Ω
R_ISO
MAX1191
22Ω
INA-
C_IN
5pF
COM
A_V = 6V/V
V_COM = V_DD/2
R_ISO
22Ω
INA+
C_IN
5pF
R10
600Ω
R11
600Ω
OPERATIONAL AMPLIFIERS
CHOOSE EITHER OF THE MAX4452/MAX4453/MAX4454 SINGLE/
DUAL/QUAD +3V, 200MHz OP AMPS FOR USE WITH THIS CIRCUIT.
CONNECT THE POSITIVE SUPPLY RAIL (V_CC) TO 3V. CONNECT THE
NEGATIVE SUPPLY RAIL (V_EE) TO GROUND. DECOUPLE V_CC WITH A
0.1µF CAPACITOR TO GROUND.
RESISTOR NETWORKS
RESISTOR NETWORKS ENSURE PROPER THERMAL AND TOLERANCE
MATCHING. FOR R1, R2, AND R3 USE A NETWORK SUCH AS VISHAY'S
3R MODEL NUMBER 300192. FOR R4–R11, USE A NETWORK SUCH AS
VISHAY'S 4R MODEL NUMBER 300197.
Figure 7. DC-Coupled Differential Input Driver
In idle mode, the pipeline ADCs, reference, and clock
distribution circuits are powered, but the outputs are
forced to tri-state. The wake-up time from idle mode is
dominated by the 5ns required for the output drivers to
start from tri-state. When the outputs transition from tri-
state to on, the last converted word is placed on the
digital outputs.
In the normal operating mode, all sections of the
MAX1191 are powered.
Applications Information
The circuit of Figure 7 operates from a single 3V supply
and accommodates a wide 0.5V to 1.5V input common-
mode voltage range for the analog interface between
an RF quadrature demodulator (differential, DC-cou-
pled signal source) and a high-speed ADC.
Furthermore, the circuit provides required SINAD and
SFDR to demodulate a wideband (BW = 3.84MHz),
QAM-16 communication link. R_ISO isolates the op amp
output from the ADC capacitive input to prevent ringing
and oscillation. C_IN filters high-frequency noise.
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