MAX1191 Datasheet, PDF (17/27 Pages) Maxim Integrated Products – Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
CHA
CHB
CLK
t_DOB
A/B
t_DA/B
D0–D7
t_CLK
t_CL
t_CH
t_DOA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
D0B
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
D5A
D5B
D6A
D6B
Figure 5. System Timing Diagram
provide lowest possible jitter. Any significant aperture
jitter would limit the SNR performance of the on-chip
ADCs as follows:
SNR
=
20
×

log _{ 2}
×
π
1
× f_IN
×

t_{AJ }
1111 1111
1111 1110
1111 1101
1LSB = ^{2 x VREF}
256
V_REF
V_REF = V_REFP - V_REFN
V_REF
where f_IN represents the analog input frequency and
t_AJ is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines. The MAX1191
clock input operates with a V_DD/2 voltage threshold
and accepts a 50% ±10% duty cycle (see Typical
Operating Characteristics).
System Timing Requirements
Figure 5 shows the relationship between the clock, ana-
log inputs, A/B indicator, and the resulting output data.
Channel A (CHA) and channel B (CHB) are simultane-
ously sampled on the rising edge of the clock signal
(CLK) and the resulting data is multiplexed at the out-
put. CHA data is updated on the rising edge and CHB
data is updated on the falling edge of the CLK. The A/B
indicator follows CLK with a typical delay time of 6ns
and remains high when CHA data is updated and low
when CHB data is updated. Including the delay
through the output latch, the total clock-cycle latency is
5 clock cycles for CHA and 5.5 clock cycles for CHB.
1000 0001
1000 0000
0111 1111
(COM)
0000 0011
0000 0010
0000 0001
0000 0000
-128 -127 -126 -125
-1 0 +1
(COM)
INPUT VOLTAGE (LSB)
+125 +126 +127 +128
Figure 6. Transfer Function
Digital Output Data (D0–D7),
Channel Data Indicator (A/B)
D0–D7 and A/B are TTL/CMOS-logic compatible. The
digital output coding is offset binary (Table 2, Figure 6).
The capacitive load on the digital outputs D0–D7
should be kept as low as possible (<15pF) to avoid
large digital currents feeding back into the analog por-
tion of the MAX1191 and degrading its dynamic perfor-
mance. Buffers on the digital outputs isolate them from
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