MAX1191 Datasheet, PDF(16/27 Page) Maxim Integrated Products – Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC

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MAX1191 Datasheet, PDF (16/27 Pages) Maxim Integrated Products – Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC

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Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC

Table 1. Reference Modes

VREFIN

>0.8 x VDD

1.024V Â±10%

REFERENCE MODE

Internal reference mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM

each with a 0.33ÂµF capacitor.

Buffered external reference mode. An external 1.024V Â±10% reference voltage is applied to

REFIN. VREF is internally generated to be VREFIN/2. Bypass REFP, REFN, and COM each with a

0.33ÂµF capacitor. Bypass REFIN to GND with a 0.1ÂµF capacitor.

<0.3V

Unbuffered external reference mode. REFP, REFN, and COM are driven by external reference

sources. VREF is the difference between the externally applied VREFP and VREFN. Bypass REFP,

REFN, and COM each with a 0.33ÂµF capacitor.

values originally held on C2a and C2b. These values

are then presented to the first stage quantizers and iso-

late the pipelines from the fast-changing inputs. The

wide input bandwidth T/H amplifiers allow the MAX1191

to track and sample/hold analog inputs of high frequen-

cies (>Nyquist). Both ADC inputs (INA+, INB+, INA-,

and INB-) can be driven either differentially or single

ended. Match the impedance of INA+ and INA-, as well

as INB+ and INB-, and set the common-mode voltage

to midsupply (VDD/2) for optimum performance.

Analog Inputs and Reference

Configurations

The MAX1191 full-scale analog input range is Â±VREF

with a common-mode input range of VDD/2 Â±0.2V. VREF

is the difference between VREFP and VREFN. The

MAX1191 provides three modes of reference operation.

The voltage at REFIN (VREFIN) sets the reference oper-

ation mode (Table 1).

In internal reference mode, connect REFIN to VDD or

leave REFIN unconnected. VREF is internally generated

to be 0.512V Â±3%. COM, REFP, and REFN are low-

impedance outputs with VCOM = VDD/2, VREFP = VDD/2

+ VREF/2, and VREFN = VDD/2 - VREF/2. Bypass REFP,

REFN, and COM each with a 0.33ÂµF capacitor.

In buffered external reference mode, apply a 1.024V

Â±10% at REFIN. In this mode, COM, REFP, and REFN

are low-impedance outputs with VCOM = VDD/2, VREFP =

VDD/2 + VREFIN/4, and VREFN = VDD/2 - VREFIN/4.

Bypass REFP, REFN, and COM each with a 0.33ÂµF

capacitor. Bypass REFIN to GND with a 0.1ÂµF capacitor.

In unbuffered external reference mode, connect REFIN

to GND. This deactivates the on-chip reference buffers

for COM, REFP, and REFN. With their buffers shut

down, these nodes become high-impedance inputs

(Figure 4) and can be driven through separate, external

reference sources. Drive VCOM to VDD/2 Â±10%, drive

MAX1191

62.5ÂµA

REFP

4kâ¦

0ÂµA

COM

4kâ¦

REFN

62.5ÂµA

1.75V

1.5V

1.25V

Figure 4. Unbuffered External Reference Mode Impedance

VREFP to (VDD/2 +0.256V) Â±10%, and drive VREFN to

(VDD/2 - 0.256V) Â±10%. Bypass REFP, REFN, and COM

each with a 0.33ÂµF capacitor.

For detailed circuit suggestions and how to drive this

dual ADC in buffered/unbuffered external reference

mode, see the Applications Information section.

Clock Input (CLK)

CLK accepts a CMOS-compatible signal level. Since

the interstage conversion of the device depends on the

repeatability of the rising and falling edges of the exter-

nal clock, use a clock with low jitter and fast rise and

fall times (<2ns). In particular, sampling occurs on the

rising edge of the clock signal, requiring this edge to

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