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MAX11040_10 Datasheet, PDF (5/32 Pages) Maxim Integrated Products – 24-Bit, 4-Channel, Simultaneous-Sampling,Cascadable,Sigma-Delta ADC
24-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADC
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO =
CREF0 = CREF1 = CREF2 = CREF3 = 1µF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
SYNC Pulse Width
tSYN
XIN
2
Clock
Cycles
XIN Clock Pulse Width
DRDYIN to DRDYOUT
XIN Clock to DRDYOUT Delay
XIN Clock Period
XIN Clock to SYNC Setup
SYNC to XIN Clock Hold
XIN to CLKOUT Delay
Power-On Reset Delay
tXPW
tDRDY
tXDRDY
tXP
tSS
tHS
tXCD
CLOAD = 30pF
DRDYIN = DGND
(Note 12)
(Note 12)
(Note 13)
16
ns
20
ns
40
ns
40
ns
16
ns
5
ns
40
ns
<1
ms
Note 1: Devices are production tested at +105°C. Specifications to -40°C are guaranteed by design.
Note 2: Tested at VAVDD = VDVDD = +3.0V.
Note 3: Integral nonlinearity is the deviation of the analog value at any code from its ideal value after the offset and gain errors are
removed.
Note 4: Offset nulled.
Note 5: Offset and gain drift defined as change in offset and gain error vs. full scale.
Note 6: Noise measured with AIN_+ = AIN_- = AGND.
Note 7: Relative accuracy is defined as the difference between the actual RMS amplitude and the ideal RMS amplitude of a 62.5Hz
sine wave, measured over one cycle at a 16ksps data rate, expressed as a fraction of the ideal RMS amplitude. The rela-
tive accuracy specification refers to the maximum error expected over 1 million measurements. Calculated from SNR. Not
production tested.
Note 8: Latency is a function of the sampling rate and XIN clock. See the Latency section in the Digital Filter section.
Note 9: Voltage levels below the positive fault threshold and above the negative fault threshold, relative to AGND on each individ-
ual AIN_+ and AIN_- input, do not trigger the analog input protection circuitry.
Note 10: Test performed using RXD MP35.
Note 11: All digital inputs at DGND or DVDD.
Note 12: SYNC is captured by the subsequent XIN clock if this specification is violated.
Note 13: Delay from DVDD exceeds 2.0V until digital interface is operational.
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