MAX11040_10 Datasheet, PDF (4/32 Pages) Maxim Integrated Products – 24-Bit, 4-Channel, Simultaneous-Sampling,Cascadable,Sigma-Delta ADC

24-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADC
ELECTRICAL CHARACTERISTICS (continued)
(V_AVDD = +3.0V to +3.6V, V_DVDD = +2.7V to V_AVDD, f_{XIN CLOCK} = 24.576MHz, f_OUT = 16ksps, V_REFIO = +2.5V (external), C_REFIO =
C_REF0 = C_REF1 = C_REF2 = C_REF3 = 1µF to AGND, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
CMOS DIGITAL OUTPUTS (DOUT, CASCOUT, DRDYOUT, CLKOUT)
Output Low Voltage
VOL I_SINK = 5mA
Output High Voltage
VOH I_SOURCE = 1mA
Three-State Leakage Current
ILT
Three-State Capacitance
COUT
OPEN-DRAIN DIGITAL OUTPUTS (OVRFLW, FAULT)
0.85 x
V_DVDD
Output Low Voltage
VOL I_SINK = 5mA
Output High Voltage
Internal Pullup Resistance
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Current (Note 11)
VOH
AVDD
DVDD
IAVDD
Digital Supply Current (Note 11)
IDVDD
AC Positive-Supply Rejection
DC Positive-Supply Rejection
ESD PROTECTION
All Pins
ESD
TIMING CHARACTERISTICS (Figures 7–10)
SCLK Clock Period
tSCP
SCLK Pulse Width (High and Low)
tPW
DIN or CS to SCLK Fall Setup
tSU
SCLK Fall to DIN or CS Hold
tHD
SCLK Rise to DOUT Valid
tDOT
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
CASCIN to SCLK Rise Setup
SCLK Rise to CASCOUT Valid
tDOE
tDOD
tCSW
tSC
tCOT
Internal pullup only
0.85 x
V_DVDD
3.0
2.7
Normal operation
Shutdown and f_XINCLOCK = 0Hz
Normal operation
Shutdown and f_XINCLOCK = 0Hz
V_AVDD = 3.3V + 100mV_P-P at 1kHz
V_AVDD = V_DVDD = 3.0V to 3.6V
Human Body Model
50
20
10
0
CLOAD = 30pF
1.5
CLOAD = 100pF
CLOAD = 30pF
0.3
CLOAD = 30pF
0.7
16
16
CLOAD = 100pF
TYP MAX UNITS
0.15 x
V
V_DVDD
V
±1
μA
15
pF
0.15 x
V_DVDD
V
V
30
k

3.6
V
V_AVDD
V
25
35
mA
0.1
5
μA
11
15
mA
0.3
μA
70
dB
75
dB
2.5
kV
ns
ns
ns
ns
10
16
ns
< 16
20
ns
16
ns
ns
ns
20
ns
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