MAX11040_10 Datasheet, PDF (23/32 Pages) Maxim Integrated Products – 24-Bit, 4-Channel, Simultaneous-Sampling,Cascadable,Sigma-Delta ADC

24-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADC
There are two ways to use a single line to indicate that
all MAX11040s have their data ready, depending on
whether or not they are clocked synchronously. If all
MAX11040s have the same XIN clock and have been
synchronized using SYNC or reset commands, the
DRDYOUT of any device in the chain is used to repre-
sent all of them. Alternatively, if the devices use a differ-
ent XIN clock, connect DRDYIN of device 0 to ground,
and connect DRDYIN of device n to the DRDYOUT of
device n-1 for all devices. DRDYOUT does not go low
until DRDIN is low and the conversion of the device is
complete. In this configuration, DRDYOUT of the last
device goes low only when all devices in the chain have
their data ready.
t_CSW
CS
DIN
SCLK
DOUT
CASCOUT0
(CASCIN0 = 0)
CASCOUT1
CASCOUT2
CASCOUT3
DEVICE 0 DEVICE 1 DEVICE 2 DEVICE 3 DEVICE 4 DEVICE 5 DEVICE 6 DEVICE 7
CASCOUT4
CASCOUT5
CASCOUT6
CASCOUT7
Figure 13. Configuration Register Read Operation Timing Diagram for Eight Cascaded Devices
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