MAX11040_10 Datasheet, PDF(10/32 Page) Maxim Integrated Products – 24-Bit, 4-Channel, Simultaneous-Sampling,Cascadable,Sigma-Delta ADC

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MAX11040_10 Datasheet, PDF (10/32 Pages) Maxim Integrated Products – 24-Bit, 4-Channel, Simultaneous-Sampling,Cascadable,Sigma-Delta ADC

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24-Bit, 4-Channel, Simultaneous-Sampling,

Cascadable, Sigma-Delta ADC

Typical Operating Circuit

1Î¼F 3.3V

3.3V 1Î¼F

AIN0+

AIN0-

1Î¼F

AIN1+

AIN1-

1Î¼F

AIN2+

AIN2-

1Î¼F

AIN3+

AIN3-

1Î¼F

0.01Î¼F

AIN0+

AIN0-

REF0

AVDD

0.01Î¼F

DVDD

XIN

XOUT

AIN1+

AIN1-

REF1

MAX11040 CLKOUT

CASCOUT

CASCIN

AIN2+

AIN2-

REF2

AIN3+

AIN3-

REF3

REFIO

AGND

OVRFLW

FAULT

SCLK

DIN

DOUT

SYNC

DRDYOUT

DRDYIN

DGND

20pF

24.576MHz

20pF

MICROCONTROLLER

OR DSP

Detailed Description

The MAX11040 is a 24-bit, simultaneous-sampling,

4-channel, sigma-delta ADC including support for syn-

chronized sampling and daisy chaining of the serial

interface across multiple (up to eight) MAX11040

devices. The serial interface of the set of synchronized

devices behaves as one device. Each channel includes

a differential analog input, a sigma-delta modulator, a

digital decimation filter, an independent programmable

sampling delay, and a buffered reference signal from

the internal or an external reference. The device con-

tains an internal crystal oscillator. The output data rate,

the effective sample rate of the ADC, is software pro-

grammable.

The MAX11040 operates from a single 3.0V to 3.6V

analog supply and a 2.7V to VAVDD digital supply. The

4-wire serial interface is SPI/QSPI/MICROWIRE and

DSP compatible.

ADC Modulator

Each channel of the MAX11040 performs analog-to-

digital conversion on its input using a dedicated

switched-capacitor sigma-delta modulator. The modula-

tor converts the input signal into low-resolution digital data

for which the average value represents the digitized sig-

nal information at 3.072Msps for a 24.576MHz XIN clock.

This data stream is then presented to the digital filter for

processing to remove the high-frequency noise that cre-

ates a high-resolution 24-bit output data stream.

The input sampling network of the analog input consists

of a pair of 4pF capacitors (CSAMPLE), the bottom

plates of which are connected to AIN_+ and AIN_- dur-

ing the track phase and then shorted together during

the hold phase (see Figure 1). The internal switches

24.576MHz XIN clock, the switching frequency is

3.072MHz. The sampling phase lasts for 120ns.

AIN_+

MAX11040

TRACK

CSAMPLE+

AIN_-

HOLD

TRACK

CSAMPLE-

RON

TO ADC

RON

AVDD/2

Figure 1. Simplified Track/Hold Stage

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