MAX11040_10 Datasheet, PDF (19/32 Pages) Maxim Integrated Products – 24-Bit, 4-Channel, Simultaneous-Sampling,Cascadable,Sigma-Delta ADC

24-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADC
CS
DIN
SCLK
DOUT
CASCOUT0
(CASCIN0 = 0)
CASCOUT1
DRDYOUT0
(DRDYIN0 = 0)
DRDYOUT1
24 CYCLES 24 CYCLES 24 CYCLES 24 CYCLES 24 CYCLES 24 CYCLES 24 CYCLES 24 CYCLES
CHANNEL 0,
DEVICE 0
CHANNEL 1,
DEVICE 0
CHANNEL 2,
DEVICE 0
CHANNEL 3,
DEVICE 0
CHANNEL 0,
DEVICE 1
CHANNEL 1,
DEVICE 1
CHANNEL 2,
DEVICE 1
CHANNEL 3,
DEVICE 1
DEVICE 1 TAKES OVER SPI BUS
DEVICE 0 DATA READY
DEVICE 0 AND DEVICE 1 DATA READY
Figure 11. 192-Bit Data Read Operation Diagram for Two Cascaded Devices
Data Rate Control Register
The Data Rate Control register controls the output data
period, which corresponds to the output data rate of
the ADC. The data period is controlled by both a
coarse (FSAMPC[2:0]) and a fine (FSAMPF[10:0])
adjustment (see Table 7).
The final data rate is derived by dividing the XIN clock
frequency by a divider value. The divider value is a
function of FSAMPC[2:0] and FSAMPF[10:0]:
Data Rate = f_XINCLOCK/Divider
Divider = Coarse Cycle Factor x 384 + Fine Cycle
Factor x FSAMPF[10:0]
Note: Fractional results for the divider are rounded
down to the nearest integer. Coarse cycle factor and
fine cycle factor come from Table 7. The effect of
FSAMPF[10:0] in the formula has limitations as noted in
the table.
Examples of output data rate vs. FSAMPC[2:0] and
FSAMPF[10:0] are shown in Table 8. Table 9 shows typi-
cal device performance for various data rate settings.
The data length of the Data Rate Control register is 16
bits total for writes and reads (see Table 2). Changes to
the Data Rate Control register take effect within one con-
version period.
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