MAX11040_10 Datasheet, PDF (30/32 Pages) Maxim Integrated Products – 24-Bit, 4-Channel, Simultaneous-Sampling,Cascadable,Sigma-Delta ADC

24-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADC
To compensate the result of an FFT for the MAX11040
output data:
1) Calculate the inverse (1/x) of the equation provided
in the Digital Filter section for each frequency in the
FFT.
2) Multiply the FFT of the MAX11040 output data by the
result of the above step.
Power Supplies
AVDD and DVDD provide power to the MAX11040. The
AVDD powers up the analog section, while the DVDD
powers up the digital section. The power supply for
AVDD and DVDD ranges from +3.0V to +3.6V and 2.7V
to V_AVDD, respectively. Bypass AVDD to AGND with a
1µF electrolytic capacitor in parallel with a 0.1µF ceramic
capacitor and bypass DVDD to DGND with a 1µF elec-
trolytic capacitor in parallel with a 0.1µF ceramic capaci-
tor. For improved performance, place the bypass
capacitors as close as possible to the device.
Layout, Grounding, and Bypassing
The best layout and grounding design always comes
from a thorough analysis of the complete system. This
includes the signal source’s dependence and sensitivi-
ty on ground currents, and knowledge of the various
currents that could travel through the various potential
grounding paths.
Use PCBs with separate analog and digital ground
planes. Connect the two ground planes together only at
the MAX11040 GND input. Isolate the digital supply
from the analog with a low-value resistor (10Ω) or ferrite
bead when the analog and digital supplies come from
the same source.
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PCB
ground trace impedance of only 0.05Ω creates an error
voltage of approximately 250µV.
Ensure that digital and analog signal lines are kept sepa-
rate. Do not run digital (especially the SCLK and DOUT)
lines parallel to any analog lines or under the MAX11040.
Layout the traces in perpendicular directions when a dig-
ital line and an analog line cross each other.
Bypass AVDD to the analog ground plane with a 0.1µF
capacitor in parallel with a 1µF to 10µF low-ESR capac-
itor. Keep capacitor leads short for best supply-noise
rejection. Bypass REF+ and REF- with a 0.1µF capaci-
tor to GND. Place all bypass capacitors as close as
possible to the device for optimum decoupling.
Crystal Layout
Follow these basic layout guidelines when placing a
crystal on a PCB with a MAX11040 to avoid coupled
noise:
1) Place the crystal as close as possible to XIN and
XOUT. Keeping the trace lengths between the crys-
tal and inputs as short as possible reduces the
probability of noise coupling by reducing the length
of the “antennae.” Keep the XIN and XOUT lines
close to each other to minimize the loop area of the
clock lines. Keeping the trace lengths short also
decreases the amount of stray capacitance.
2) Keep the crystal solder pads and trace width to XIN
and XOUT as small as possible. The larger these
bond pads and traces are, the more likely it is that
noise will couple from adjacent signals.
3) Place a guard ring (connect to ground) around the
crystal to isolate the crystal from noise coupled from
adjacent signals.
4) Ensure that no signals on other PCB layers run
directly below the crystal or below the traces to XIN
and XOUT. The more the crystal is isolated from
other signals on the board, the less likely for noise to
couple into the crystal.
5) Place a local ground plane on the PCB layer imme-
diately below the crystal guard ring. This helps to
isolate the crystal from noise coupling from signals
on other PCB layers.
Note: Keep the ground plane in the vicinity of the
crystal only and not on the entire board.
PROCESS: BiCMOS
Chip Information
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