MAX11040K_1111 Datasheet, PDF (5/35 Pages) Maxim Integrated Products – 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs

24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V_AVDD = +3.0V to +3.6V, V_DVDD = +2.7V to V_AVDD, f_{XIN CLOCK} = 24.576MHz, f_OUT = 16ksps, V_REFIO = +2.5V (external), C_REFIO =
C_REF0 = C_REF1 = C_REF2 = C_REF3 = 1μF to AGND, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.) (Note 1)
PARAMETER
SCLK Rise to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
CASCIN-to-SCLK Rise Setup
SCLK Rise to CASCOUT Valid
SYNC Pulse Width
XIN Clock Pulse Width
DRDYIN to DRDYOUT
XIN Clock to DRDYOUT Delay
XIN Clock Period
XIN Clock to SYNC Setup
SYNC to XIN Clock Hold
XIN-to-CLKOUT Delay
Power-On Reset Delay
SYMBOL
t_DOT
t_DOE
t_DOD
t_CSW
t_SC
t_COT
CONDITIONS
C_LOAD = 30pF
C_LOAD = 100pF
C_LOAD = 30pF
C_LOAD = 30pF
C_LOAD = 100pF
t_SYN
t_XPW
t_DRDY
t_XDRDY
t_XP
t_SS
t_HS
t_XCD
C_LOAD = 30pF
DRDYIN = DGND
(Note 12)
(Note 12)
(Note 13)
MIN
TYP
MAX UNITS
1.5
10
16
ns
< 16
0.3
20
ns
0.7
16
ns
16
ns
16
ns
20
ns
XIN
2
Clock
Cycles
16
ns
20
ns
40
ns
40
ns
16
ns
5
ns
40
ns
<1
ms
Note 1: Devices are production tested at +105°C. Specifications to -40°C are guaranteed by design.
Note 2: Tested at V_AVDD = V_DVDD = +3.0V.
Note 3: Integral nonlinearity is the deviation of the analog value at any code from its ideal value after the offset and gain errors are
removed.
Note 4: Offset nulled.
Note 5: Offset and gain drift defined as change in offset and gain error vs. full scale.
Note 6: Noise measured with AIN_+ = AIN_- = AGND.
Note 7: Relative accuracy is defined as the difference between the actual RMS amplitude and the ideal RMS amplitude of a 62.5Hz
sine wave, measured over one cycle at a 16ksps data rate, expressed as a fraction of the ideal RMS amplitude. The rela-
tive accuracy specification refers to the maximum error expected over 1 million measurements. Calculated from SNR. Not
production tested.
Note 8: Latency is a function of the sampling rate and XIN clock.
Note 9: Voltage levels below the positive fault threshold and above the negative fault threshold, relative to AGND on each individ-
ual AIN_+ and AIN_- input, do not trigger the analog input protection circuitry.
Note 10: Test performed using RXD MP35.
Note 11: All digital inputs at DGND or DVDD.
Note 12: SYNC is captured by the subsequent XIN clock if this specification is violated.
Note 13: Delay from DVDD exceeds 2.0V until digital interface is operational.
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