MAX11040K_1111 Datasheet, PDF (18/35 Pages) Maxim Integrated Products – 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs

24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
SCLK
CASCOUT
(DEVICE n)
CASCIN
(DEVICE n+1)
t_COT
t_SC
Figure 9. CASCIN and CASCOUT Timing Diagram
t_XP
t_XPW
XIN CLOCK
t_XCD
CLKOUT
t_HS
t_SS
SYNC
t_SYN
DRDYOUT
t_XDRDY
Figure 10. XIN Clock, CLKOUT, SYNC, and DRDYOUT Timing
Diagram
Registers
The devices include four registers accessible by 7
command bytes. The command bytes provide read
and write access to the Data Rate Control register, the
Sampling Instant Control register, and the Configuration
register, and read access to the Data register. See
Table 2. Figure 9 shows the CASCIN and CASOUT
timing diagram. Figure 10 is the XIN clock, CLKOUT,
SYNC, and DRDYOUT timing diagram.
Table 2. Command Bytes
R/W ^ADDRESS
DATA
[A6:A0] LENGTH*
FUNCTION
0
1000000
32 x n** bits
Write Sampling Instant
Control Register
1
1000000
32 x n bits
Read Sampling Instant
Control Register
0
1010000
16 bits ^{Write Data-Rate Control}
Register
1
1010000
16 bits ^{Read Data-Rate Control}
Register
0
1100000 8 x n bits ^{Write Configuration}
Register
1
1100000 8 x n bits ^{Read Configuration}
Register
1
1110000 96 x n bits Read Data Register
*All data lengths are proportional to the number of cascaded
devices except for reads and writes to the Data Rate Control
register. When accessing the Data Rate Control register, the
data length is fixed at 16 bits. These 16 bits are automatically
written to all cascaded devices.
**n is the total number of cascaded devices.
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