MAX11040K_1111 Datasheet, PDF (23/35 Pages) Maxim Integrated Products – 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs

24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Table 8. Data-Rate Control Register
BITS
[15:13]
[12:11]
[10:0]
NAME
FSAMPC[2:0]
Reserved
FSAMPF[10:0]
DESCRIPTION
Output data rate coarse adjust bits. FSAMPC[2:0] sets the coarse cycle factor.
FSAMPC
000
001
010
011
100
101
110
111
Set to 0.
Coarse Cycle
Factor
4
128
64
32
16
8
2
1
Sample Rate in ksps
(f_{XIN CLOCK} = 24.576MHz)
16
0.5
1
2
4
8
32
64
Output data rate fine adjusts bits. FSAMPF[10:0] increases the output data period by a number of
XIN clock cycles. This number is the value of the register times the fine cycle factor. Values of
FSAMPF greater than 1535 have no additional effect.
FSAMPC
000
001
010
011
100
101
110
111
XIN Fine Cycle Factor
1 cycle
32 cycles
16 cycles
8 cycles
4 cycles
2 cycles
1 cycle
1 cycle
Table 9. Examples of Output Data Rate as a Function of FSAMPC[2:0] and FSAMPF[10:0]
FSAMPC[2:0] FSAMPF[10:0]
OUTPUT DATA
RATE (sps)
11xxxxxxxxx
250.1
10111111111
001
00000000001
250.1
499.7
00000000000
500.0
11xxxxxxxxx
500.2
10111111111
010
00000000001
500.2
999.3
00000000000
1000.0
11xxxxxxxxx
1000.3
10111111111
1000.3
011
00000000001
1998.7
00000000000
2000.0
OUTPUT DATA PERIOD
(24.576MHz CLOCK CYCLES)
98272
98272
49184
49152
49136
49136
24592
24576
24568
24568
12296
12288
FSAMPF OUTPUT DATA PERIOD
RESOLUTION
(24.576MHz CLOCK CYCLES)
32
16
8
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