MAX11040K_1111 Datasheet, PDF (12/35 Pages) Maxim Integrated Products – 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs

24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Typical Operating Circuit
1µF ^3.3V
3.3V _1µF
AIN0+
AIN0-
1µF
AIN1+
AIN1-
1µF
AIN2+
AIN2-
1µF
AIN3+
AIN3-
1µF
1µF
0.01µF
AIN0+
AIN0-
REF0
AVDD
0.01µF
DVDD
XIN
XOUT
AIN1+
AIN1-
REF1
MAX11040K ^CLKOUT
MAX11060 _CASCOUT
CASCIN
AIN2+
AIN2-
REF2
AIN3+
AIN3-
REF3
REFIO
AGND
OVRFLW
FAULT
CS
SCLK
DIN
DOUT
SYNC
DRDYOUT
DRDYIN
DGND
20pF
24.576MHz
20pF
MICROCONTROLLER
OR DSP
Detailed Description
The MAX11040K/MAX11060 are 24-/16-bit, simultane-
ous-sampling, 4-channel, sigma-delta ADCs including
support for synchronized sampling and daisy chaining
of the serial interface across multiple (up to eight)
devices. The serial interface of the set of synchronized
devices behaves as one device. Each channel includes
a differential analog input, a sigma-delta modulator, a
digital decimation filter, an independent programmable
sampling delay, and a buffered reference signal from
the internal or an external reference. The device con-
tains an internal crystal oscillator. The output data rate,
the effective sample rate of the ADC, is software pro-
grammable.
The devices operate from a single 3.0V to 3.6V analog
supply and a 2.7V to V_AVDD digital supply. The 4-wire
serial interface is SPI/QSPI/MICROWIRE and DSP com-
patible.
ADC Modulator
Each channel of the devices performs analog-to-
digital conversion on its input using a dedicated
switched-capacitor sigma-delta modulator. The modula-
tor converts the input signal into low-resolution digital data
for which the average value represents the digitized sig-
nal information at 3.072Msps for a 24.576MHz XIN clock.
This data stream is then presented to the digital filter for
processing to remove the high-frequency noise that cre-
ates a high-resolution 24-/16-bit output data stream.
The input sampling network of the analog input consists
of a pair of 4pF capacitors (C_SAMPLE), the bottom
plates of which are connected to AIN_+ and AIN_- dur-
ing the track phase and then shorted together during
the hold phase (see Figure 1). The internal switches
have a total series resistance of 400Ω. Given a
24.576MHz XIN clock, the switching frequency is
3.072MHz. The sampling phase lasts for 120ns.
AIN_+
TRACK
MAX11040K
MAX11060
C_SAMPLE+
AIN_-
HOLD
TRACK
C_SAMPLE-
R_ON
TO ADC
R_ON
AVDD/2
Figure 1. Simplified Track/Hold Stage
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